Semiconductor Energy Laboratory Co., Ltd.

Takanori Matsuzaki

Kiyoshi Kato

Hiroki Inoue

Shuhei Nagatsuka

Tatsuya Onuki

Shunpei Yamazaki

Munehiro Kozuma

Yuki Okamoto

Yutaka Shionoiri

Jun Koyama

Hajime Kimura

Takayuki Ikeda

Takeshi Osada

Tomoaki Atsumi

Takahiko Ishizu

Satoru Okamoto

Junya Maruyama

Ryota Tajima

Kazuo Nishi

Kei Takahashi

Toshihiko Saito

Daisuke Matsubayashi

Yoshinobu Asami

Hitoshi Kunitake

Mayumi Mikami

Minato Ito

Toru Takayama

Hideki Uochi

Yohei Momma

Yuto Yakubo

Eiji Sugiyama

Ryosuke Watanabe

Masafumi Morisue

Susumu Okazaki

Hiromichi Godo

Susumu Kawashima

Hidetomo Kobayashi

Kazutaka Kuriki

Atsushi Miyaguchi

Takeshi Aoki

Yutaka Okazaki

Masashi Oota

Ryota Hodo

Ryo Tokumaru

Kosei Nei

Kazuki Tsuda

Akio Suzuki

Toshiki Hamada

Seiya Saito

Yusuke Koumura

A battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including either of the battery circuits are provided. The power storage device includes a first circuit portion, a second circuit portion, a third circuit portion, and a secondary battery; the first circuit portion has a function of controlling charging of the secondary battery; the first circuit portion has a function of supplying the start time and the end time of the charging of the secondary battery to the third circuit portion; the second circuit portion has functions of generating a first voltage and a first current and supplying them to the third circuit portion; the third circuit portion has a function of generating a second voltage by charging the first current in a capacitor; and the third circuit portion has a function of comparing the first voltage and the second voltage.

Power storage device and method for operating power storage device

A novel semiconductor device that is highly convenient or reliable is provided. The semiconductor device includes a sensor unit, a first memory unit, a second memory unit, and a determination unit. The sensor unit supplies a sensor signal, the first memory unit retains the sensor signal, the second memory unit retains standard data and allowable difference information, the determination unit compares the sensor signal with the standard data, and the determination unit supplies a control signal in the case where a difference between the sensor signal and the standard data exceeds the allowable difference information.

Semiconductor device sensor unit

A semiconductor device with high reliability is provided. The semiconductor device includes a memory cell including a first ferroelectric capacitor and a reference memory cell including a second ferroelectric capacitor. In a first period, first binary data is written to the memory cell, and first reference binary data is written to the reference memory cell. In a second period, the first binary data is read from the memory cell, and the first reference binary data is read from the reference memory cell. In a third period, logic operation of the first binary data and the first reference binary data is performed. In a fourth period, second binary data is written to the memory cell, and second reference binary data is written to the reference memory cell. A value of the first binary data and a value of the second binary data are different from each other, and a value of the first reference binary data and a value of the second reference binary data are different from each other.

Driving method of semiconductor device

A display apparatus with a novel structure is provided. The display apparatus includes a first layer and a second layer positioned above the first layer. The first layer includes a driver circuit region, and the second layer includes a pixel array. The pixel array includes a plurality of pixel regions. The driver circuit region includes a control circuit unit and a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to any one of the plurality of pixel regions. The local driver circuit has a function of outputting a driving signal for driving a plurality of pixels included in the corresponding pixel region. The control circuit unit has a function of comparing definition data of an input image signal and aspect ratio data of the pixel array to determine a first region where display is performed and a second region where display is not performed, and outputting, to the local driver circuit corresponding to the second region, a control signal for stopping output of the driving signal.

Display apparatus and electronic device

To provide a semiconductor device with a novel structure. The semiconductor device includes an accelerator. The accelerator includes a first memory circuit, a second memory circuit, and an arithmetic circuit. The first memory circuit includes a first transistor. The second memory circuit includes a second transistor. Each of the first transistor and the second transistor includes a semiconductor layer including a metal oxide in a channel formation region. The arithmetic circuit includes a third transistor. The third transistor includes a semiconductor layer including silicon in a channel formation region. The first transistor and the second transistor are provided in different layers. The layer including the first transistor is provided over a layer including the third transistor. The layer including the second transistor is provided over the layer including the first transistor. The data retention characteristics of the first memory circuit are different from those of the second memory circuit.

Semiconductor device

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

Display device and electronic device

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Semiconductor device, display apparatus, and electronic device

A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Memory device

A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a transistor, a first and a second conductor, and a first to a third insulator. The transistor and the first conductor are provided over the first insulator. The transistor includes an oxide semiconductor. The second insulator is provided over the transistor. The first conductor includes a region which does not overlap with the second insulator. The third insulator is provided to cover the first conductor, the transistor, and the second insulator. The second conductor is provided over the third insulator and at least partly overlaps with the first conductor.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Semiconductor device and method of manufacturing semiconductor device

A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

Semiconductor device and electronic device

A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

Semiconductor device, memory device, and electronic device

The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M), the second switch (M) and the first capacitor (C) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M), the second capacitor (C) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M) and a drain of the second transistor (M), a gate of the second transistor is electrically connected to the fifth switch (M), the third capacitor (C) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element ().

Semiconductor device and method for driving semiconductor device

A semiconductor device having a large storage capacity is provided. The semiconductor device includes an oxide provided over a substrate, a plurality of first conductors over the oxide, a first insulator that is provided over the plurality of first conductors and includes a plurality of openings overlapping with regions between the plurality of first conductors, a plurality of second insulators provided in the respective plurality of openings, a plurality of charge retention layers provided over the respective plurality of second insulators, a plurality of third insulators provided over the respective plurality of charge retention layers, and a plurality of second conductors provided over the respective plurality of third insulators.

Semiconductor device using oxide and method for manufacturing semiconductor device using oxide

Growing community of inventors

Kanagawa, Japan

Takanori Matsuzaki