Semiconductor Energy Laboratory Co., Ltd.

Takanori Matsuzaki

Kiyoshi Kato

Hiroki Inoue

Shuhei Nagatsuka

Tatsuya Onuki

Shunpei Yamazaki

Yutaka Shionoiri

Jun Koyama

Yuki Okamoto

Munehiro Kozuma

Hajime Kimura

Takeshi Osada

Tomoaki Atsumi

Takahiko Ishizu

Takayuki Ikeda

Satoru Okamoto

Junya Maruyama

Kazuo Nishi

Toshihiko Saito

Kei Takahashi

Ryota Tajima

Daisuke Matsubayashi

Yoshinobu Asami

Toru Takayama

Hideki Uochi

Yuto Yakubo

Hitoshi Kunitake

Mayumi Mikami

Eiji Sugiyama

Ryosuke Watanabe

Masafumi Morisue

Susumu Okazaki

Minato Ito

Hiromichi Godo

Susumu Kawashima

Hidetomo Kobayashi

Atsushi Miyaguchi

Yutaka Okazaki

Yohei Momma

Ryota Hodo

Ryo Tokumaru

Kosei Nei

Kazuki Tsuda

Akio Suzuki

Toshiki Hamada

Seiya Saito

A high-resolution display device in which delay of input signals to pixels is reduced is provided. In the display device, a first layer, a second layer, and a third layer are formed in this order from the bottom. The first layer includes a driver circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. The plurality of second wirings are parallel to each other and extended in the column direction of the pixel array, and the plurality of pixel circuits are electrically connected to the plurality of second wirings. The driver circuit includes a plurality of output terminals positioned along a first direction. The plurality of first wirings are extended perpendicular to the first direction, and the plurality of output terminals are electrically connected to the plurality of first wirings. The plurality of first wirings are electrically connected to the plurality of second wirings through the plurality of first contact portions.

Display device and electronic device

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Semiconductor device, display apparatus, and electronic device

A semiconductor device with a novel structure is provided. The semiconductor device includes a silicon substrate including a first circuit, a first element layer including a second circuit, and a second element layer including a third circuit. The first circuit includes a first transistor. The second circuit includes a second transistor. The third circuit includes a memory cell. The memory cell includes a third transistor and a capacitor. The first element layer and the second element layer constitute a stacked block stacked and provided in a direction perpendicular or substantially perpendicular to a surface of the silicon substrate. A plurality of stacked blocks are stacked and provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. Each of the plurality of stacked blocks includes a first wiring provided in the direction perpendicular or substantially perpendicular to the surface of the silicon substrate. The plurality of stacked blocks are electrically connected to each other through the wiring.

Semiconductor device

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. The first conductor is provided with a first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator provided therebetween. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

Memory device

A semiconductor device with less variation in transistor characteristics is provided. The semiconductor device includes a transistor, a first and a second conductor, and a first to a third insulator. The transistor and the first conductor are provided over the first insulator. The transistor includes an oxide semiconductor. The second insulator is provided over the transistor. The first conductor includes a region which does not overlap with the second insulator. The third insulator is provided to cover the first conductor, the transistor, and the second insulator. The second conductor is provided over the third insulator and at least partly overlaps with the first conductor.

Semiconductor device and method for manufacturing semiconductor device

A semiconductor device that can be miniaturized or highly integrated can be provided. The semiconductor device includes a first conductor positioned over a substrate; an oxide positioned in contact with atop surface of the first conductor; a second conductor, a third conductor, and a fourth conductor positioned over the oxide; a first insulator in which a first opening and a second opening are formed, the first insulator being positioned over the second conductor to the fourth conductor; a second insulator positioned in the first opening; a fifth conductor positioned over the second insulator; a third insulator positioned in the second opening; and a sixth conductor positioned over the third insulator. The third conductor is positioned to overlap with the first conductor. The first opening is formed to overlap with a region between the second conductor and the third conductor. The second opening is formed to overlap with a region between the third conductor and the fourth conductor.

Semiconductor device and method of manufacturing semiconductor device

A data semiconductor device with a long retention time is provided. The semiconductor device includes a first transistor, a second transistor, a ferroelectric capacitor, a first capacitor, and a memory cell. Note that the memory cell includes a third transistor. A first gate of the first transistor is electrically connected to a first terminal of the ferroelectric capacitor, and a first terminal of the first transistor is electrically connected to a second gate of the first transistor and a first terminal of the second transistor. A second terminal of the second transistor is electrically connected to a second terminal of the ferroelectric capacitor and a first terminal of the first capacitor. A back gate of the third transistor is electrically connected to the first terminal of the first transistor. In the above structure, the threshold voltage of the third transistor can be increased by supplying a negative potential to the first terminal of the first transistor.

Semiconductor device and electronic device

A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

Semiconductor device, memory device, and electronic device

The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element. The first transistor (M) comprises a back gate, a gate of the first transistor is electrically connected to the first switch (M), the second switch (M) and the first capacitor (C) are positioned between the gate of the first transistor and a source of the first transistor, the back gate of the first transistor is electrically connected to the third switch (M), the second capacitor (C) is positioned between the back gate of the first transistor and the source of the first transistor, the source of the first transistor is electrically connected to the fourth switch (M) and a drain of the second transistor (M), a gate of the second transistor is electrically connected to the fifth switch (M), the third capacitor (C) is positioned between the gate of the second transistor and a source of the second transistor, and the source of the second transistor is electrically connected to the display element ().

Semiconductor device and method for driving semiconductor device

A semiconductor device having a large storage capacity is provided. The semiconductor device includes an oxide provided over a substrate, a plurality of first conductors over the oxide, a first insulator that is provided over the plurality of first conductors and includes a plurality of openings overlapping with regions between the plurality of first conductors, a plurality of second insulators provided in the respective plurality of openings, a plurality of charge retention layers provided over the respective plurality of second insulators, a plurality of third insulators provided over the respective plurality of charge retention layers, and a plurality of second conductors provided over the respective plurality of third insulators.

Semiconductor device using oxide and method for manufacturing semiconductor device using oxide

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of arithmetic blocks each including an arithmetic circuit portion and a memory circuit portion. The arithmetic circuit portion and the memory circuit portion are electrically connected to each other. The arithmetic circuit portion and the memory circuit portion have an overlap region. The arithmetic circuit portion includes, for example, a Si transistor, and the memory circuit portion includes, for example, an OS transistor. The arithmetic circuit portion has a function of performing product-sum operation. The memory circuit portion has a function of retaining weight data. A first driver circuit has a function of writing the weight data to the memory circuit portion. The weight data is written to all the memory circuit portions included in the same column with the use of the first driver circuit.

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Imaging device and electronic device

A highly reliable memory device is provided. On a side surface of a first conductor extending in a first direction, a first insulator, a first semiconductor, a second insulator, a second semiconductor, and a third insulator are provided in this order when seen from the first conductor side. A first region overlapping with a second conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween, and a second region overlapping with a third conductor with the first insulator, the first semiconductor, the second insulator, the second semiconductor, and the third insulator therebetween are provided in the first conductor. In the second region, a fourth conductor is provided between the first insulator and the first semiconductor.

A first transistor, a second transistor, a capacitor, and first to third conductors are included. The first transistor includes a first gate, a source, and a drain. The second transistor includes a second gate, a third gate over the second gate, first and second low-resistance regions, and an oxide sandwiched between the second gate and the third gate. The capacitor includes a first electrode, a second electrode, and an insulator sandwiched therebetween. The first low-resistance region overlaps with the first gate. The first conductor is electrically connected to the first gate and is connected to a bottom surface of the first low-resistance region. The capacitor overlaps with the first low-resistance region. The second conductor is electrically connected to the drain. The third conductor overlaps with the second conductor and is connected to the second conductor and a side surface of the second low-resistance region.

The safety is ensured in such a manner that with an abnormality detection system of a secondary battery, abnormality of a secondary battery is detected, for example, a phenomenon that lowers the safety of the secondary battery is detected early, and a user is warned or the use of the secondary battery is stopped. The abnormality detection system of the secondary battery determines whether the temperature of the secondary battery is within a temperature range in which normal operation can be performed on the basis of temperature data obtained with a temperature sensor. In the case where the temperature of the secondary battery is high, a cooling device is driven by a control signal from the abnormality detection system of the secondary battery. The abnormality detection system of the secondary battery includes at least a memory means. The memory means has a function of holding an analog signal and includes a transistor using an oxide semiconductor for a semiconductor layer.

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Kanagawa, Japan

Takanori Matsuzaki