Fujitsu Corporation

Takanori Ishii

Shinnosuke Matsuda

Kentarou Yuasa

Nina Tsukamoto

Sadayuki Ohyama

Tomoyuki Kanayama

Yohei Nuno

Tatsuya Shinozaki

Yuji Hanaoka

Yoko Kawano

Nina Arataki

Tomoharu Muro

Keisuke Yamasaki

Kazuko Sasaki

Yoshiharu Watanabe

Ryo Kubota

Kazuko Sakurai

Kentaro Yuasa

Tomoka Aoki

Yoko Okuno

An information processing system includes a plurality of control apparatuses communicably coupled to each other. A first control apparatus of the plurality of control apparatuses includes a first memory configured to store first instructions and a first processor configured to operate using standby power before a power-on selection is made. The first processor executes the first instructions causing a process including collecting first identification information of each of the plurality of control apparatuses other than the first control apparatus. The process includes storing the first identification information in the first memory. The process includes determining a role of the first control apparatus based on a comparison result derived by comparing second identification information of the first control apparatus with the first identification information.

Information processing system and control apparatus

A storing unit stores therein mapping management information indicating mappings between each of a plurality of divided regions created by dividing logical storage space on a storage apparatus and one of a plurality of identification numbers each representing a different write frequency. A control unit measures the write frequency of each of the plurality of divided regions and updates the mappings indicated by the mapping management information based on results of the write frequency measurement. Upon request for a data write to a write address included in a divided region after the update of the mappings, the control unit identifies an identification number associated with the divided region based on the mapping management information, appends the identified identification number to a write request for the write address, and transmits the write request with the identified identification number appended thereto to the storage apparatus.

Storage control apparatus and computer-readable storage medium storing storage control program

An information processing apparatus includes a communication apparatus and a different communication apparatus connected to the communication apparatus via a plurality of transmission paths. The communication apparatus includes a transmitting unit and a control unit. In response to designation of a transmission path targeted for diagnosis, selected amongst the transmission paths while the communication apparatus is in a state capable of data communication with the different communication apparatus using the transmission paths, the transmitting unit transmits a test signal to the targeted transmission path while the state capable of data communication with the different communication apparatus is maintained using remaining transmission paths of the transmission paths other than the targeted transmission path. The control unit diagnoses the presence or absence of an abnormality sign in the targeted transmission path based on the result of detecting the test signal in the targeted transmission path and outputs the diagnostic result.

Information processing apparatus, diagnosis control apparatus, and communication apparatus

A storage control device includes a first processor, a second processor, and transfer units for transferring data from the first processor to the second processor. The first processor receives a write request for writing first data from a first device and sequentially transmits the first data, additional data, and pieces of dummy data. A number of the pieces is same as a number of the transfer units. The first processor notifies the first device of completion of the writing upon receiving an acknowledgement for a last transmitted piece of dummy data. Each transfer unit includes a third processor. The third processor receives the additional data from a preceding processor, and transmits an acknowledgement to the preceding processor upon storing the received additional data. The third processor receives one piece of dummy data from the preceding processor, and transmits an acknowledgement to the preceding processor upon storing the one piece.

Storage control device

An information processing apparatus includes: an interface unit that communicates with another device through a plurality of physical links; a setting unit that determines a value of a setting parameter for setting a signal transmission characteristic for each of the plurality of physical links by performing a negotiation with the other device and that outputs a plurality of determined values of the setting parameter, each of the plurality of determined values corresponding to one of the plurality of physical links; and a judgment unit that judges whether each of the plurality of determined values is correct or not by judging whether or not a difference between a maximum value and a minimum value among the plurality of determined values falls within a predetermined range.

Information processing apparatus, storage system, and computer-readable non-transitory storage medium storing communication control program

A processing apparatus includes a first memory, a second memory, a capacitor, and a processor coupled to the first memory and the second memory. The processor is configured to cause power feeding from the capacitor, and execute a first processing to cause the first memory to hold data, after the power feeding is caused from the capacitor, cause a battery to start power feeding in at least one of a case where the power feeding from an external power source is not started after being halted and an output voltage of the capacitor has fallen below a first value, and a case where the power feeding from the external power source is not started after being halted and a first time period has elapsed, and execute a second processing to write the data from the first memory into the second memory during the power feeding from the battery.

Processing apparatus, method, and non-transitory computer-readable storage medium

There is provided a control device which includes a cache memory configured to temporarily store data, a nonvolatile memory configured to store a copy of the data stored in the cache memory, a battery configured to supply power to the cache memory in a case of a power failure, a data save processing unit configured to save data stored in a backup target region of the cache memory to the nonvolatile memory in the case of the power failure, and a charge control unit configured to charge the battery up to a target amount of charge which is determined on the basis of a size of the backup target region.

Control device, power supply device, and method for controlling power

An information processing apparatus includes a battery for providing the interior of the information processing apparatus with power; a volatile memory for storing data; a nonvolatile memory for backupping the data stored in the volatile memory; a controller for controlling backup of the data in accordance with a process comprising the steps of: saving the data into the nonvolatile memory; upon recovery of the power from the external power source, writing back the data into the volatile memory; and deleting the data saved in the nonvolatile memory; wherein when the power from an external power source to the information processing apparatus is stopped during deleting data in the nonvolatile memory, the controller selectively writes back deleted data from the volatile memory into the nonvolatile memory.

Information processing apparatus and data backup method

According to an aspect of the embodiment, in a control method for a disk array apparatus, a CPU of a first control module acquires other system state information, which is decided based on a battery and a nonvolatile memory of the second control module and indicates a data saving possibility of a cache memory of a second control module. The CPU of the first control module determines, based on the other system state information acquired and own system state information, which is decided based on a battery and a nonvolatile memory of the first control module and indicates a data saving possibility of a cache memory of the first control module, whether the disk array apparatus is set in a write-back state or a write-through state.

Control method for disk array apparatus and disk array apparatus

An information processing apparatus includes a controller, a plurality of electric power supply units and a backup electric power supply unit that supply electric power to the controller. The controller detects a malfunction occurring in the plurality of electric power supply units, stops electric power supply from the plurality of electric power supply units, starts electric power supply from the backup electric power supply unit when a malfunction is detected, identifies an electric power supply unit having a malfunction from the plurality of electric power supply units, disconnects the identified electric power supply unit, resumes electric power supply from an electric power supply unit determined to function normally and stops the electric power supply from the backup electric power supply unit when the electric power supply unit having the malfunction is disconnected.

Information processing apparatus, control apparatus, and method

A transfer-indication storage unit indicates an address and a data length of data to be transferred by a DMA circuit. An expected value table refers to a transfer indication of the transfer-indication storage unit and stores therein expected values of the address and the data length of the data to be transferred. A transfer-monitoring unit retrieves tag data and a data length of data in a bus. Based on the data length and the tag data notified by the transfer-monitoring unit, a table updating unit updates a start address and the data length in the expected value table. A determining unit determines whether the start address, corresponding to the DMA circuit after data transfer, matches with an end address, and further determines whether the data length has become zero.

Monitoring device, semiconductor integrated circuit, and monitoring method

A backup method makes a backup of cache data to a nonvolatile memory by using a controller, the cache data being stored in the volatile memory. The backup method includes writing the cache data stored in the volatility memory in a selected area of the nonvolatile memory, generating party data by operating the parity operations between each of the predetermined parts of the cache data in the volatile memory, verifying whether an error found in the part of the cache data in the nonvolatile memory can be recovered by using the parity data, and rewriting the part of the cache data when the error found in the part of the cache data in the nonvolatile memory cannot be recovered by using the parity data in an area of the nonvolatile memory different from the selected area.

Backup method and disk array apparatus

A storage system includes a housing, a cooling unit cooling the interior of the housing, and a plurality of control units adapted to control the cooling unit. The control units each include a mount state acquisition unit acquiring a mount state of the control unit in the housing, an operation state acquisition unit acquiring an operation state of the cooling unit, and a determining unit determining a provisional main control unit, from among the plurality of control units, that is operable to control the entire cooling unit based on information acquired from the mount state acquisition unit and the operation state acquisition unit.

Storage system, storage system control method and storage system control apparatus

In an LSI implemented by a DMA chip, a BCC check block performs BCC check of cache data each time the cache data is read. In response to a check result indicating whether or not the check is completed, a CM read block turns on a BCC check bit and a BCC error bit of a data-transfer-end notification. Further, an FCC check block performs FCC check of the cache data. In response to a check result indicating whether or not the check is completed, the CM read block turns on an FCC check bit and an FCC error bit of the data-transfer-end notification. When data transfer is finished, the CM read block sends the data-transfer-end notification to a CPU via a descriptor block.

Data access method, channel adapter, and data access control device

A storage controlling apparatus controlling an access, for example, from a host to a physical device has a determining means determining whether or not a basic mode predetermined among two or more modes agrees with a mode set in a mode setting sequence run when the apparatus is reset or when data is transferred between modules, and a notifying means determining that transfer mode abnormality occurs when the determining means determines that the two modes do not agree with each other and sending an error notice. Whereby, a data transfer status in a mode differing from the basic mode can be detected as transfer mode abnormality, and the transfer mode abnormality can be solved.

Apparatus having a transfer mode abnormality detecting function, storage controlling apparatus, and interface module for the storage controlling apparatus

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Kawasaki, Japan

Takanori Ishii