Hitachi, Ltd.

Renesas Technology Corp.

Renesas Electronics Corporation

Takanobu Tsunoda

Osamu Nishii

Tetsuya Yamada

Masashi Takada

Sadaki Nakano

Naohiko Irie

Takahiro Irita

Hiroshi Tanaka

Kiyoto Ito

Motonobu Tonomura

Masayuki Kabasawa

Tomoichi Hayashi

Fumio Arakawa

Makoto Saen

Norio Nakagawa

Koji Hosogi

Manabu Kawabe

Yohei Akita

Bryan Atwood

Tetsuro Honmura

Keisuke Toyama

Tetsuroo Honmura

Makoto Sato

It has been difficult to carry out a test and an analysis with respect to combinational logic circuits mounted across plural chips, and therefore, there is provided a flip-flop () by use of which either of a scan chain within a semiconductor chip (LSI_B), and a scan chain across plural semiconductor chips (LSI_A and LSI_B) can be made up.

Semiconductor device, and test method for same

A highly flexible semiconductor device of a stacked-type semiconductor device which transfers information by inductive coupling between inductors, in which LSI chips can be stacked even when a transmitter circuit and a receiver circuit are arranged at different positions from each other when viewed in a stacking direction. The semiconductor device has an interposer including a first inductor which is inductively coupled with a transmitter circuit of a first LSI chip to be stacked, and a second inductor which is inductively coupled with a receiver circuit of a second LSI chip to be stacked, the first inductor and the second inductor being electrically connected. An interchip communication is made from the first LSI chip to the second LSI chip.

Semiconductor device

This invention provide a data processor capable of multiplexing data transfers with desired data transfer characteristics guaranteed, without multiplexing buses. The data processor includes: a transfer path that mutually connects plural processors and plural transfer element circuits such as memory; an arbitration circuit that controls data transfer in the transfer path; and a control register that defines the priority and minimum guaranteed bandwidth of data transfer. The arbitration circuit decomposes data packets sent from plural data transfer sources into subunits, and reconstructs plural data packets having the same data transfer target, based on priority and minimum guaranteed bandwidth stored in a control register. Thereby, the one reconstructed data packet can include subunits of plural data packets from transfer sources having different priorities, and data amounts of subunits contained in it can satisfy minimum guaranteed bandwidth of data transfer.

Data processor and semiconductor integrated circuits

There is provided at least one processor block including a plurality of load store interfaces (), a plurality of memory banks (), an input/output port having at least one of an input port () and an output port (), and a crossbar switch (), and the crossbar switch connects the load store interface, the memory bank and the input/output port to each other and the load store interface constitutes a data processor in order to control a data transfer to the memory bank. Consequently, there is implemented a data processor having a high transfer throughput and a flexibility and efficiently treating stream data.

Data processor with internal memory structure for processing stream data

To realize a software radio processing with a reduced circuit area by hardware and software which can process transmission and reception, or synchronization and demodulation in time division. There are provided a circuit DRC that can dynamically change a configuration with a structure that can change the configuration at a high speed, a general processor, and an interface for connection with an external device such as an AD converter or a DA converter. Software radio is realized by using a software radio chip that conducts plural different processing such as transmission and reception, or synchronization and demodulation in time division. The different processing during the radio signal processing can be conducted in time division. As a result, the software radio can be realized with a circuit of a reduced area in a software radio system that allocates regions of an FPGA to the respective processing.

Semiconductor integrated circuit and a software radio device

A dynamically reconfigurable processor is provided having a wiring structure which enables flexible mapping of a program to the processor with a small wiring area. A first wire permits a first arrangement of circuit blocks and a second wire provided for changing the arrangement order of the circuit blocks. A switch is provided to switch between the first wire and the second wire. By virtue of this arrangement, a greater variety of calculations can be performed in the circuit without the necessity for increasing the number of operation blocks.

Dynamically reconfigurable processor and processor control program for controlling the same

A basic cell capable of a fixed operating frequency regardless of the configuration information, which is also capable of effectively utilizing the arithmetic logic circuit within the cell in a LSI semiconductor integrated circuit, is capable of dynamic changes in configuration information. The circuit has an input switch ISW connected to multiple data input nodes, an output switch OSW connected to multiple data output nodes, a first data path containing an arithmetic logic circuit ALU and a result storage flip-flop CFFbetween the input switch ISW and output switch OSW. The second data path containing a data transfer flip-flop between an input switch ISW and an output switch OSW, and the result storage flip-flop CFF stores the calculated result data from the arithmetic logic circuit ALU, and the data transfer flip-flop holds data input from any of the multiple data input nodes.

Semiconductor integrated circuit including multiple basic cells formed in arrays

A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.

Method and apparatus for event detection for multiple instruction-set processor

A microprocessor includes a first cache memory, a first instruction fetch unit, a first instruction decoder, a first processing unit and a first latch that holds a control signal outputted from the first instruction decoder. When the first instruction fetch unit receives a first instruction performed by the first processing unit it outputs the first instruction to the first instruction decoder. When the first instruction fetch unit receives a second instruction which is not performed by the first processing unit, it outputs a specific instruction to the first instruction decoder, after which the supply of clock pulses to other latch circuits In the first processing unit is halted based on the control signal.

Halting clock signals to input and result latches in processing path upon fetching of instruction not supported

The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths Pand Pare formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the Pside is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.

Hardware accelerator for a platform-independent code

A microprocessor to reduce wasteful power consumption of the floating-point unit. An instruction invalidation logic circuit is utilized to substitute the instruction not-to-use-the-floating-point unit, in the instruction string supplied from the instruction cache, with an invalidating instruction, hold that invalidating instruction in the floating-point register, and supply that invalidating instruction to a floating-point decoder in the floating-point unit. In cases when the invalidating instruction was continuous, the power consumption in the floating-point data path as well as the in the floating-point decoder and floating-point register is reduced.

Substituting specified instruction with NOP to functional unit and halting clock pulses to data latches for power saving

A system LSI including substrate-bias generation circuits for supplying substrate biases independent of each other to functional modules integrated in the system LSI, a substrate-bias control circuit for controlling the substrate-bias generation circuits and a substrate-bias control-value storage unit for storing control values to be supplied to the substrate-bias generation circuits. The control values stored in the substrate-bias control-value storage unit are set by carrying out a predetermined operation. As a result, it is possible to provide a device for implementing both a high-speed operation and low power consumption without lowering the yield and for finely controlling the power consumption during the operation.

System LSI having a substrate-bias generation circuit with a substrate-bias control-value storage unit

A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is provided. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

Semiconductor integrated circuit device and information processing device employing semiconductor integrated circuit device

A small-area associative memory for association by a value resulted from addition, with reduced carry delay, is disclosed. Adjacent 1-bit memory values and a signal depending on adjacent 2 bits of addition-inputs are inputted into a CAM memory cell constructed using MOS transistors, and a hit line is pulled down or pulled up in accordance with the input values.

The data processor includes a CPU and an instruction prefetch buffer that prefetches an instruction executed by the CPU and stores it therein. The CPU contains a detection circuit for detecting whether or not a displacement from a branch instruction to a branch target instruction is a specific displacement on the basis of branch displacement information that the concerned branch instruction holds. The instruction prefetch buffer clears an instruction already prefetched when the detection circuit detects that the displacement is not the specific displacement and outputs a branch target instruction newly fetched to the CPU, and outputs a branch target instruction already prefetched to the CPU when the detection circuit detects that the displacement is the specific displacement. Thus, the date processor fetches a branch target instruction within a certain range from the instruction prefetch buffer at a high speed without adding the nullifying bit on the instruction code.

Growing community of inventors

Kokubunji, Japan

Takanobu Tsunoda