Renesas Electronics Corporation

Renesas Technology Corp.

Hitachi, Ltd.

Murata Manufacturing Co., Ltd.

Hitachi Ulsi Systems Co., Ltd.

Takanobu Naruse

Chiaki Fujii

Tadashi Kameyama

Fumie Katsuki

Shinichi Yoshioka

Hirotaka Hara

Yohei Akita

Takashi Sato

Seiichi Saito

Hisashi Shiota

Shigezumi Matsui

Motoo Suwa

Yoshinori Miyaki

Takayasu Ito

Norio Nakagawa

Hirohiko Ito

Hajime Sasaki

Toru Hayashi

Bernard Ramanadin

Atsushi Hasegawa

Takashi Ichimura

Vijaya Pratap Adusumilli

Ryoichi Sano

Kenichiro Omura

Hirokatsu Noguchi

Kazuhide Kawade

Yoshiyuki Matsumoto

Ryohei Yoshida

Shikiko Nachi

A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

Semiconductor device and electronic device

A monitor circuit includes a reference voltage generating unit that generates first and second reference voltages, a first amplifier unit that amplifies a differential voltage between the first reference voltage and the second reference voltage, a second amplifier unit that amplifies a differential voltage between an internal power supply voltage being supplied to a functional block provided in the semiconductor integrated circuit and the first reference voltage, and a comparator unit that compares an amplification result of the first amplifier unit with an amplification result of the second amplifier unit and outputs a comparison result as a measurement result.

Monitor circuit, semiconductor integrated circuit, semiconductor device, and method of controlling power supply voltage of semiconductor device

A temperature sensor in a semiconductor device includes a temperature detection circuit for outputting a voltage according to the chip temperature, a reference voltage generating circuit for generating a plurality of reference voltages, and a plurality of voltage comparators for comparing each reference voltage with an output voltage of the temperature detection circuit and thereby generating a chip temperature detection signal configured with multiple bits. Further, the temperature sensor includes a control circuit for controlling the reference voltages generated by the reference voltage generating circuit based on the chip temperature detection signal and thereby changing correspondence between the chip temperature detection signal and the chip temperature to shift a chip temperature detection range. It is possible to expand the chip temperature detection range by changing the correspondence between the chip temperature detection signal and the chip temperature, without increasing the number of voltage comparators.

Semiconductor device and temperature sensor system

A semiconductor device includes a clock input circuit that receives an external clock signal, a PLL circuit for input timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to acquire input data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to a PLL circuit for input timing control as a delayed clock signal. The semiconductor device further includes a PLL circuit for output timing control that performs phase adjustment between the external clock signal and a delayed clock signal to generate an internal clock signal used to output output data, and a delay circuit that delays the internal clock signal to output the internal clock signal that is delayed to the PLL circuit for output timing control as a delayed clock signal.

In a wiring substrate, a double data rate (DDR) memory and a memory controller controlling the DDR memory are mounted. Further, in the wiring substrate, plural equal-length wires connecting the DDR memory and the memory controller are formed. The plural equal-length wires include a differential transmission line, such as a clock wire transmitting a clock signal, which is connected via a common mode choke coil. The differential transmission line may have a wire length shorter than a wire length of another equal-length wire, by a wire length corresponding to delay time of a transmission signal due to the common mode choke coil.

Wiring substrate in which equal-length wires are formed

The data processor enhances the bus throughput or data throughput of an external memory, when there are frequent continuous reads with a smaller data size than the data bus width of the external memory. The data processor includes a memory control unit being capable of controlling in response to a clock an external memory having plural banks that are individually independently controllable, plural buses connected to the memory control unit, and circuit modules capable of commanding memory accesses, which are provided in correspondence with each of the buses. The memory control unit contains bank caches each corresponding to the banks of the external memory. Thereby, the data processor enhances the bus throughput or data throughput of the external memory, since the data processor stores the data read out from the external memory temporarily in the bank caches and to use the stored data without invalidating them, when performing a continuous data read with a smaller data size than the data bus width of the external memory.

Data processor

Data processor having a memory controller with cache memory

An electronic circuit includes a first semiconductor device and a second semiconductor device on a mounting substrate. The mounting substrate lines have lengths which are made unequal for respective bits. Assembling lines which reach connecting electrodes of a semiconductor chip from the external terminals of the second semiconductor device have made lengths thereof unequal for respective bits. The unequal lengths of the mounting substrate lines have a relationship which offsets the unequal lengths of the assembling lines.

Electronic circuit, a semiconductor device and a mounting substrate

Data processor having a memory control unit with cache memory

It is aimed at providing a data processor capable of suppressing a sudden current change from the viewpoint of a synchronization clock. A data processorcomprises a clock pulse generation circuit and a circuit module operating on input clock signal CLKi output from the clock pulse generation circuit. In case of restoration from a power-on reset period or a standby state, the clock pulse generation circuit stepwise changes frequencies of the clock signal from low to high frequencies. This makes it possible to prevent a power supply current from suddenly increasing in case of restoration from the power-on reset period or the standby state.

A DMA controller including a request queue for holding DMA transfer requests clears only the request queue without executing unnecessary DMA transfers and provides information about the states of the queue. A DMA controller is configured to enable data transfer control with respect to plural channels and includes a request queue capable of holding the identification information of channels concerned in plural data transfer requests, wherein the states of the request queue can be outputted and information held in the request queue can be cleared.

Data transfer control circuit with terminal sharing

A computer system having a simple handshake protocol for implementing DMA transfers. A system bus is provided having a plurality of ports for coupling to system components including memory, central processing unit(s) and peripherals. A direct memory access controller (DMAC) is provided with a peripheral-independent interface coupled to the system bus and communicates with the system bus using system bus defined transactions. The DMAC comprises a set of registers. A central processing unit (CPU) configures teh DMAC by loading values into the DMAC registers. The configured DMAC issues an enable signal to a selected system component identified in the DMAC registers. A peripheral request interface is associated with the selected system components and communicates with the system bus using the system bus defined transactions. The selected system component asserts a request signal to the DMAC. In response to the request signal, the DMAC implements a DMA transfer according to the values stored in the DMAC configuration registers. Peripheral-specific signaling is provided to the system component by the peripheral request interface

DMA handshake protocol

Growing community of inventors

Tokyo, Japan

Takanobu Naruse