Fuji Xerox Co., Ltd.

Takane Satoh

Yoichi Tan

A timing synchronization circuit for use in a multi-station communication system in which one station is a master station. The timing synchronization circuit within each station comprises a clock operating at a frequency nearly constant between the stations. The clock signal is frequency-divided to provide synchronization of the frames and blocks of the data being transmitted. The clock signal is reinitialized by a reset signal generated when a packet of data transmitted by the master station is received and recognized by the station by identifying code within the packet. The reinitialization accounts for the propagation delays relative to the master station.

Timing synchronization circuit

For coupling a digital signal between two asynchronous transmission paths, an asynchronous connecting device includes a serial-to-parallel converter for converting the digital signal into parallel words, a first latch for latching the parallel words at a rate synchronized to the first transmission path, a second latch for latching the output of the first latch at a rate synchronized to the second transmission path, and a parallel-to-serial converter for converting the output of the second latch into a serial digital signal to be transmitted along the second transmission path. It is preferable that the sampling rate of the second latch be higher than that of the first latch, and it is also possible to smooth the second latch output prior to converting it to serial data.

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Kanagawa, Japan

Takane Satoh