Renesas Electronics Corporation

Renesas Technology Corp.

Takamitsu Kanazawa

Yukihiro Sato

Toshiyuki Hata

Hiroyoshi Taya

Katsuhiko Funatsu

Masahiro Koido

Satoru Akiyama

Ryo Kanda

Akira Muto

Koji Bando

Michitaka Osawa

Takeshi Otani

Kazuhiro Mitamura

Akihiro Tamura

Kuniharu Muto

Hirobumi Minegishi

Reduction in reliability of a semiconductor device is suppressed. A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a plurality of semiconductor chips mounted on the plurality of metal patterns. Also, the plurality of metal patterns include metal patterns MPH and MPU which face each other. In addition, a region which is provided between these metal patterns MPH and MPU and which is exposed from the plurality of metal patterns extends so as to zigzag along an extending direction of the metal pattern MPH.

Semiconductor device with metal patterns having convex and concave sides

To improve the reliability of a semiconductor device. A chip mounting portion TABis arranged to be shifted to the +x direction side. Further, a gate electrode pad of a semiconductor chip CHP(LV) and a pad of a semiconductor chip CHPare electrically coupled by a wire Wand a wire Wthrough a relay lead RL. Likewise, a gate electrode pad of a semiconductor chip CHP(LW) and the pad of the semiconductor chip CHPare electrically coupled by a wire Wand a wire Wthrough a relay lead RL. At this time, the structures of parts of the relay leads RLand RL, which are exposed from a sealing body MR are different from the structures of respective parts exposed from the sealing body MR, of a plurality of leads LDand LDwhich function as external terminals.

Semiconductor device

Reliability of a semiconductor device is improved. A third semiconductor chip on which a control circuit is formed, and a first semiconductor chip of a plurality of IGBT chips are electrically connected via a high-side relay board. That is, the first semiconductor chip and the third semiconductor chip are electrically connected via a first wire, a high-side relay board and a second wire. Similarly, the third semiconductor chip on which the control circuit is formed and a second semiconductor chip of a plurality of IGBT chips are electrically connected via a low-side relay board. That is, the second semiconductor chip and the third semiconductor chip are electrically connected via the first wire, the low-side relay board and the second wire.

Semiconductor module

Power module with a plurality of patterns with convex and concave side

A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.

For example, a semiconductor device has a lead connected to a second portion of a chip mounting part on which a semiconductor chip to be a heat source is mounted and a lead connected to a third portion of the chip mounting part on which the semiconductor chip to be the heat source is mounted. Further, each of the leads has a protruding portion protruding from a sealing member. In this manner, it is possible to enhance a heat dissipation characteristic of the semiconductor device.

Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHPis disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.

Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Semiconductor device with normally off and normally on transistors

A semiconductor device in which the wiring resistance and parasitic inductance of a semiconductor package configuring a power semiconductor module is reduced. In the semiconductor device, a semiconductor chip with an IGBT formed therein and a diode chip are mounted over the upper surface of a die pad. An emitter pad of the semiconductor chip and an anode pad of the diode chip are coupled with a lead by an Al wire. One end of the lead is located in a higher position than the upper surface of the die pad in order to shorten the length of the Al wire for coupling the emitter pad and the lead.

A first semiconductor element having a junction electrode to be connected to a first node of a bidirectional switch circuit is mounted on a first metal base plate to be a heat dissipation plate, and a second semiconductor element having a junction electrode to be connected to a second node of the bidirectional switch circuit is mounted on a second metal base plate to be a heat dissipation plate. The junction electrode of the first semiconductor element has the same potential as that of the first metal base plate, and the junction electrode of the second semiconductor element has the same potential as that of the second metal base plate. Also, the respective metal base plates and non-junction electrodes of the respective semiconductor elements are connected by metal thin wires, respectively, thereby configuring the bidirectional switch circuit.

Growing community of inventors

Tokyo, Japan

Takamitsu Kanazawa