Japan Display Inc.

Japan Display Central Inc.

Takamitsu Fujimoto

Kenji Harada

Tetsuya Iizuka

Takahiro Oonuma

In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.

Liquid crystal display device

According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a power source voltage of high level, and a third pad to supply a necessary signal for displaying an image, a common line, a first connection line to connect the first pad with the common line, a second connection line to connect the second pad with the common line, and a third connection line to connect the third pad with the common line, wherein the first connection line and the second connection line are formed of polysilicon in which no impurity is doped, and the third connection line and the common line are formed of polysilicon in which an impurity is doped.

Display device

According to one embodiment, a liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, scanning lines, signal lines, pixel switches, first electrodes, a scanning line drive circuit, a second electrode, a voltage supply wiring, a control mechanism, a first switching mechanism, a second switching mechanism, and an output timing switching mechanism. The output timing switching mechanism is configured to simultaneously output a second scanning signal of switching the pixel switch into conductive state to the scanning lines, based on the control signal.

Growing community of inventors

Ishikawa-ken, Japan

Takamitsu Fujimoto