Kabushiki Kaisha Toshiba

Takamichi Arizono

Kazuhiro Yamada

Shigeo Ohshima

Kiminobu Suzuki

A layout-data generation equipment includes a logic circuit designing section which designs a logic circuit based on information of the specifications of a semiconductor integrated circuit, a layout-data generation section which creates layout-data based on the logic circuit, a resistance information extraction section which extracts resistance information of a wire from the layout-data, a circuit simulation execution section which executes a circuit simulation, an identification section of current direction which identifies a direction of a current in the wire based on the resistance information of a wire and an execution result of the circuit simulation, a verification section which verifies whether layout-data of the wire breaks a design rule, the design rule being extracted from the information of the specifications of a semiconductor integrated circuit and the verification section generates this verification result, and a data output section which outputs the layout-data.

Layout data generation equipment of semiconductor integrated circuit, data generation method and manufacturing method of semiconductor device

The layout making equipment of a semiconductor integrated circuit is provided with a logic circuit schematic design section that design a logic circuit diagram, based on a specification data on a circuit, a layout data creation section that creates a layout data, based on the logic circuit diagram, a logic connection verification section that verifies whether or not a data on potentials inputted in nodes of the devices and nodes of connections between the devices extracted from the layout data match a data on the logic circuit diagram, thereby to create the results, a layout data verification section that verifies whether or not the layout data violates a design rule extracted from the specification data on the circuit, based on the data on the potentials inputted in the nodes of the devices and the nodes of the connections between the devices extracted in the logic connection verification section, thereby to create the verification results, and a data output section that outputs the created layout data.

Layout making equipment of semiconductor integrated circuit, method of making layout of semiconductor integrated circuit and process of manufacture of semiconductor device

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Kamakura, Japan

Takamichi Arizono