Nec Corporation

Takami Hiruma

Hitoshi Mitani

Hidetaka Natsume

Nolifumi Sato

Norifumi Sato

Shinji Ohara

A semiconductor device having a semiconductor substrate, an impurity diffused layer formed in a principal surface of the semiconductor substrate, a conductive member formed on the semiconductor substrate adjacent to the impurity diffused layer and having a sloped surface inclined to the principal surface of the semiconductor substrate, an insulator film deposited to cover the impurity diffused layer and the conductive member, and a common contact hole formed through the insulator film to extend over a surface of the impurity diffused layer and the sloped surface of the conductive member.

Common contact hole structure in semiconductor device

The invention provides a method of fabricating a semiconductor device, including the steps of (a) forming an impurity region at a surface of a silicon substrate, (b) depositing an insulative film over the silicon substrate, (c) forming a contact hole through the insulative film to expose the impurity region of the silicon substrate, (d) forming an electrode wiring over the contact hole, the electrode wiring comprising a refractory metal silicide film and a silicon film overlying on the metal silicide film, the metal silicide film overlying the exposed impurity region, (e) depositing a second insulative film over a resultant, (f) depositing a polysilicon film on the second insulative film, (g) patterning the polysilicon film to form an element, and (h) heat-treating a resultant at high temperature in oxidizing atmosphere. The step (h) is to be carried out at any time after the step (f) has been completed. In the method, even if a semiconductor device is heat-treated at high temperature in oxidizing atmosphere, there occurs no voids in the silicon substrate below the refractory metal silicide film. This is because silicon atoms are supplied from the silicon film overlying on the refractory metal silicide film to the metal silicide film. Thus, reliable electrical connection between the electrode wiring and the silicon substrate is ensured.

Method of fabricating semiconductor device including high temperature

In an SRAM cell including two cross-coupled inverters each having a first resistance element and a drive MOS transistor, a second resistance element is connected between the first and the drive MOS transistor. A gate electrode of the drive MOS transistor of one of the inverters is connected between the first and second resistance elements of the other.

Soft error suppressing resistance load type SRAM cell

A semiconductor device according to the present invention has misregistration detecting marks provided in the periphery of a semiconductor chip. The misregistration detecting marks consist of a first scale mark for detecting misalignment in a first direction, a second scale mark for detecting misalignment in a second direction perpendicular to the first direction, and a third scale mark for detecting misalignment in a third direction making respectively specified angles with the first direction and the second direction.

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Tokyo, Japan

Takami Hiruma