Renesas Electronics Corporation

Nec Electronics Corporation

Renesas Electronic Coporation

Takamasa Itou

Takashi Ogura

Masashige Moritoki

Takayuki Iwaki

Kana Shimizu

Tatsuya Usami

Hidemitsu Aoki

Kenichi Yamamoto

Takeshi Takeda

Hiroaki Tomimori

Satoshi Kodama

Yorinobu Kunimune

Tomoko Matsuda

Mieko Hasegawa

Satoshi Itou

Shigeaki Shimizu

Kousei Ushijima

Takashi Shimane

Kazumi Saito

Katsuro Tateyama

Tsutomu Himukai

Shuuichirou Ueno

A conductor provided in an interconnection layer is allowed to have a low resistance. An insulator film is provided over a substrate, and is comprised of SiON(where x&#x3e;0.5 in an XRD analysis result). An interconnection is provided over the insulator film, and includes a first layer and a second layer. The first layer includes at least one of TiN, TaN, WN, and RuN. The second layer is provided over the first layer, and is formed of a material having a resistance lower than the first layer, for example, W.

Semiconductor device

A lower electrode includes a metal-containing oxide layer having a thickness of 2 nm or less on the surface layer. A metal-containing oxide layer is formed by oxidizing the surface of the lower electrode. A dielectric film includes a first phase appearing at room temperature in the bulk state and a second phase appearing at a higher temperature than that in the first phase in the bulk state. The second phase has a higher relative permittivity than that of the first phase.

Semiconductor device and method of manufacturing semiconductor device

To provide a structure of a semiconductor device that realizes an increase in a capacitor capacitance of a memory circuit to the maximum while inhibiting an increase in a contact resistance of a logic circuit, and a manufacture method thereof. When designating the number of layers of the local interconnect layers having wiring that makes up a logic circuit area as M and designating the number of layers of the local interconnect layers having wiring that makes up the memory circuit as N (M and N are natural numbers and satisfy M&#x3e;N), capacitance elements are provided over the interconnect layers comprised of (M&#x2212;N) layers or (M&#x2212;N+1) layers.

Semiconductor device and method for manufacturing the same

An increase of the via resistance resulted due to the presence of the altered layer that has been formed and grown after the formation of the via hole can be effectively prevented, thereby providing an improved reliability of the semiconductor device. A method includes: forming a TiN film on the semiconductor substrate; forming an interlayer insulating film on a surface of the TiN film; forming a resist film on a surface of the interlayer insulating film; etching the semiconductor substrate having the resist film formed thereon to form an opening, thereby partially exposing the TiN film; plasma-processing the exposed portion of the TiN film to remove an altered layer formed in the exposed portion of the TiN film; and stripping the resist film via a high temperature-plasma processing.

Method for manufacturing semiconductor device to form a via hole

The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnectcomprises a silicon-lower concentration regionand a silicon solid solution layerdisposed thereon. The silicon solid solution layerhas a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnectto be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layerhas the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.

Semiconductor device and method for manufacturing same

Method for manufacturing a semiconductor device, includes: forming a layer of dicobalt monosilicide (CoSi) or of cobalt (Co) on a device-forming surface of a silicon substrate in a sputter apparatus, by utilizing a predetermined temperature profile; elevating a temperature of the silicon substrate to a predetermined temperature T, which is equal to or higher than 600&#xb0; C., conducted after forming the layer of Co or CoSi; and forming a layer of monocobalt monosilicide (CoSi) on the device-forming surface of the silicon substrate at a temperature equal to or higher than T, conducted after heating the silicon substrate to T, wherein, the silicon substrate is elevated to a temperature between a highest reachable temperature Tof the silicon substrate during forming the layer of Co or CoSi and the temperature Tat a temperature ramp rate of equal to or higher than 50&#xb0; C./sec.

Method of manufacturing semiconductor device

Growing community of inventors

Kanagawa, Japan

Takamasa Itou