Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Takamaro Mizoguchi

Nobuyuki Toyoda

Akimichi Hojo

Toshiyuki Terada

Yasuo Ikawa

Katsue Kanazawa

A gate array integrated circuit in which gate cells are each composed of a DCFL circuit using Schottky-barrier FETs. A plurality of basic gate cells is arrayed in one direction to form a basic cell array, and such basic cell arrays are arranged parallel to each other. VDD lines and GND lines are provided to apply an operating voltage to the basic gate cells. In order to stably operate the gate array integrated circuit of DCFL structure in which the logical amplitude and noise margin are small, the VDD lines and the GND lines are arranged perpendicular to each other such that the number of the basic gate cells which are connected to each of the VDD lines is larger than that of the basic gate cells which are connected to each of the GND lines. According to this layout, the potential difference (voltage drop) developed in the GND lines by operation current is reduced.

Gate array integrated circuit using Schottky-barrier FETs

A Schottky gate FET is fabricated by forming on a semiconductor substrate first and second stacks facing each other. Each stack is constructed by an ohmic electrode and a spacer film. On the substrate having stacks formed thereon an insulation layer is formed and is anisotropically etched in the direction of its thickness until the planar surface portions are exposed. As a result, portions of the insulation layer remain on opposing side walls of the stacks. After removing the spacer films to define stepped portions between each remaining portion and each electrode, a layer of a metallic material capable of forming a Schottky barrier with the substrate is formed. The remaining portions are removed to pattern the metallic material layer, thereby forming a Shottky gate electrode.

Method of fabricating a Schottky gate field effect transistor

Growing community of inventors

Yokohama, Japan

Takamaro Mizoguchi