Nippon Electric Co., Ltd.

Hitachi, Ltd.

Takakuni Kuki

Toshiro Suzuki

Arata Nakagoshi

Izumi Horikawa

Takao Harakawa

Hiroyuki Tatsumi

In a mobile radio communication system employing a time-division multiple transmission scheme, having a plurality of base stations and a plurality of personal stations, an arbitrary base station, when detecting a pilot signal transmitted from any master base station in the mobile radio communication system, acts as a slave base station which does not transmit its pilot signal but transmits and receives a common control signal to and from a personal station utilizing a frequency channel occupied by the pilot signal. On the other hand, when not receiving the pilot signal, the base station searches for an available frequency channel, and acts as a master base station which transmits its pilot signal on the available frequency channel to occupy the frequency channel, and transmits and receives the common control signal to and from a personal station on that frequency channel.

Mobile radio communication system employing time division multiple

For use in deciding whether a single or a t-tuple error (t being greater than unity) is present in each bit sequence given as a primitive BCH code in accordance with a generator polynomial comprising a primitive and a non-primitive polynomial, an error checking circuit comprises first and second dividers (16, 17) for dividing each bit sequence by the primitive and the non-primitive polynomials to provide first and second signals, respectively. If the bit sequence includes only a single error, the first signal represents one of non-zero residues which result by the division when such single errors are present at the respective bit locations of the sequence. A memory (18) is preliminarily loaded with reference numbers corresponding to the respective non-zero residues and produces one of the reference numbers in response to the first signal only in the presence of a single error. A comparator (19) compares the produced reference number with a residue represented by the second signal to carry out the decision. Preferably, the memory is loaded also with the single error bit locations to locate the single error in a bit sequence being checked. The circuit may be a microcomputer operable in the above-described manner.

Circuit for checking bit errors in a received BCH code succession by the

A voltage drop detection circuit provides an accurate indication of battery voltage in an apparatus subject to large fluctuations in load current regardless of the battery internal resistance. The detection circuit periodically induces an increase in load current so as to reproduce the maximum load current drawn by the apparatus, and the resulting battery terminal voltage is compared to a fixed reference. The detection circuit finds particular utility in apparatus designed to use a variety of battery types.

Source voltage drop detecting circuit

An error correcting decoder is disclosed which blocks correction of bits received during periods of relatively high signal intensity levels. A syndrome register and decision circuit provide error correcting bits for all bits which the sequence of input data determines to be in error. But only those data bits which occur during low levels of signal intensity are corrected.

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Tokyo, Japan

Takakuni Kuki