Kabushiki Kaisha Toshiba

Takako Mori

Hiroyuki Ibe

Osamu Kinoshita

Kazuhiko Ide

Takehiko Atsumi

Hideki Ishibashi

A time-division multiplexing apparatus time-division multiplexes, in units of m bits, each bit of n-channel digital signals (n is a natural number more than 2), transmitted in a serial manner in synchronous to transmission clock pulses of a frequency of f0, by using m channels (m is a natural number smaller than n). Serial signals supplied to n channels are respectively converted into m-bit signals by shift register blocks provided for the n channels. The same bit outputs of the blocks are supplied, as an n-bit signal, to corresponding one of latch blocks, and are latched in synchronous to latch pulses of a frequency of 1/m of f0. The outputs of the latch blocks are input to n : 1 selector blocks. One of the bit signals of the selector blocks is selectively output in accordance with gate pulses.

Time-division multiplexing apparatus

In a frame synchronization circuit, a serial data signal, which includes a frame synchronization code constituted by an M number of bits in one frame, is converted by a serial/parallel converting circuit to a parallel data signal of a 2M-1 number of bits. An M number of pattern detectors of a first synchronization detecting circuit detect the code pattern of the first block of the frame synchronization code from the parallel data signal. A selection signal generating circuit holds outputs of the pattern detectors, and outputs them as a selection signal designating the bit position allotted to the pattern detector which detects the synchronization code pattern. An output of the serial/parallel converting circuit is delayed by a time required for the above-mentioned processing, and supplied to a selector, which selectively outputs an M-bit data signal corresponding to the bit position designated by the selection signal.

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Fujisawa, Japan

Takako Mori