Sony Corporation

Takaji Ohtsu

Mitsuo Soneda

Takashi Noguchi

Toshikazu Maekawa

Ken Kutaragi

Takashi Shimada

Kenichi Inoue

Hidenobu Mochizuki

Jiro Yamaguchi

Manami Fukuzawa

Solid state image pickup device

Large amplitude pulse generating circuits

A liquid crystal matrix display device has a plurality of liquid crystal display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to compensate for crosstalk that occurs because of parasitic capacitance between the vertical transmitting lines and the liquid crystal display elements, auxiliary lines are provided for the columns of such display elements, and each has a predetermined compensating capacitance relative to its associated liquid crystal display elements. A compensating signal, which is an inverted version of the video signal, is applied in succession to the auxiliary lines to compensate for any crosstalk.

Liquid crystal matrix display device

Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element. The picture unit elements discharge a signal charge onto vertical and horizontal transmitting lines in response to vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to give the output video signal a good S/N ratio, a gain-controlled current amplifier is employed. In several embodiments, the gain-controlled amplifier includes first through fourth transistors with the base-emitter junctions of the first and second transistors and of the third and fourth transistors connected in series, with a constant current source coupled to the first transistor, controlled current sources connected to the second and third transistors, and a load device coupled to the fourth transistor. In other embodiments, the gain controlled amplifier is formed of first, second, and third current mirror circuits connected in a balanced-current arrangement. Electrically variable resistances, e.g., MOS transistors, are coupled to the output transistors of the first and second current mirror circuits to control the current gain.

Image pickup apparatus with gain controlled output amplifier

Solid-state image pickup apparatus, such as an MOS imager, has a two-dimensional array of picture element units each formed of a photo sensitive element and a gating element, and scanning circuits for supplying horizontal and vertical scanning pulses. The picture unit elements in turn discharge a signal charge onto vertical and horizontal transmitting lines in response to the vertical and horizontal scanning pulses. Then, a resulting signal current is used to develop an output video signal. In order to provide a strong output video signal with a good S/N ratio, a current mirror circuit, formed of an input transistor and an output transistor with first current-carrying electrodes joined together to a voltage reference point and with control electrodes joined together, amplifies the signal current. A second current-carrying electrode of the input transistor receives a constant current from a current source and also receives the signal current. The output transistor has a second current-carrying electrode connected to an output load. Another current source can be connected to the output transistor so that only AC current will flow to the output load. The output load can be a load capacitor associated with a pre-charging transistor, or can be a serial charge transfer device.

Image pickup apparatus

A liquid crystal matrix display device has a plurality of display elements arranged in an X-Y matrix pattern. Vertical transmitting lines are connected to all of the display elements of each column, and horizontal transmitting lines are connected to each of the display elements of each row. Each of the vertical lines is connected through an input switching element to an input circuit to receive a video input signal and a horizontal pulse generator provides sequential pulse signals to control terminals of the input switching elements. In order to improve the resolution without sacrifice of contrast, the vertical transmitting lines are arranged into groups of a predetermined number of such lines, and the input switching elements associated with the lines of each such group have their control electrodes coupled together to a respective output of the horizontal scanning pulse generator. The input circuit includes time-demultiplexing circuitry, for example, formed of sample/hold circuits, to present respective sampled versions of the input signal, staggered with respect to one another, to input electrodes of respective ones of the input switching devices of each of the groups.

In a memory type insulated gate field effect semiconductor device including a semiconductor layer of one conductivity type, a source region of the opposite conductivity type formed in the surface of the semiconductor layer, a drain region of the opposite conductivity type formed in the surface of the semiconductor layer, a gate insulating layer affixed to the surface of the semiconductor layer, and a gate electrode deposited on the surface of the gate insulating layer, the gate insulating layer has a pair of thick gate guarding portions which exist on side of the source and drain regions, and a thin memory portion intermediate between the thick gate guarding portions, and a surface impurity concentration per square centimeter of the semiconductor layer under the thick gate guarding portions is different from a surface impurity concentration per square centimeter of the semiconductor layer under the tin memory portion. The voltage difference between the threshold voltages of the semiconductor device at the memorized state and at the non-memorized state can be increased, and the read-out voltage of the semiconductor device can be reduced. The circuit design is simplified.

Growing community of inventors

Hatano, Japan

Takaji Ohtsu