International Business Machines Corporation

Renesas Electronics Corporation

Takahito Watanabe

Hiroyuki Mori

Akihiro Horibe

Risa Miyazawa

Shintaro Yamamichi

Takashi Hisada

Toyohiro Aoki

Keishi Okamoto

Kuniaki Sueoka

Yoshitaka Ushiyama

Eiji Nakamura

Keiji Matsumoto

Patrick Ruch

Chinami Marushima

An interconnected semiconductor subassembly structure includes an interconnect structure; a first semiconductor die bonded to a first portion of a top surface of the interconnect structure; a second semiconductor die bonded to a second portion of the top surface of the interconnect structure; and a resin layer located within at least a first portion of a gap between the first semiconductor die and the second semiconductor die, wherein at least one of a top surface and a bottom surface of the resin layer located within the at least first portion of the gap has a concave meniscus shape.

Multichip interconnect package

Interconnecting a first chip and a second chip includes mounting the first and second chips to a chip handler having an opening and at least one support surface. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The first surface of the first chip and the first surface of the second chip mounted to the chip handler are supported by the at least one support surface of the chip handler. The first and second chips are placed on a chip support member with the chip handler from the second surfaces. A bridge member is inserted by a bridge handler through the opening of the chip handler to place the bridge member onto the first sets of terminals of the first and second chips that are exposed from the opening.

Bonding of bridge to multiple semiconductor chips

Interconnecting a first chip and a second chip by a bridge member includes a chip handler for handling the first chip and the second chip. Each of the first chip and the second chip has a first surface including a first set of terminals and a second surface opposite to the first surface. The chip handler has an opening and at least one support surface for supporting the first surfaces of the first chip and the second chip when the first chip and the second chip are mounted to the chip handler. A chip support member supports the first chip and the second chip from the second surfaces, and a bridge handler is provided for inserting the bridge member through the opening of the chip handler and for placing the bridge member onto the first sets of terminals of the first chip and the second chip.

An integrated circuit package includes a substrate including at least one electrical connection to at least one of power or ground. The package further includes a bridge structure including at least one layer of conductive material and at least one layer of insulative material. The bridge structure is configured to be coupled to the substrate such that the conductive material is electrically connected to the at least one electrical connection. The bridge structure includes a side pad made of conductive material that is electrically connected to the at least one electrical connection. The side pad is in direct contact with the conductive material and with the insulative material of the bridge structure. The side pad forms an end face of the bridge structure such that the conductive material of the side pad is exposed.

Side pad anchored by next adjacent via

Embodiments are disclosed for a method for restoring a wearable biological sensor. The method includes determining that a wearable biological marker sensor comprising a reference electrode is placed within a restoration apparatus. The restoration apparatus includes a correct reference electrode, a counter electrode, and a chloride solution. The reference electrode is in electrical contact with the correct reference electrode and the counter electrode through the chloride solution. The method additionally includes determining whether the reference electrode is degraded based on a voltage differential between the reference electrode and the correct reference electrode. The method also includes restoring the reference electrode, if the reference electrode is degraded, by applying a voltage to a circuit. The circuit includes the reference electrode and the counter electrode. Further, multiple chloride ions of the chloride solution bond with a plurality of silver atoms of the reference electrode.

Restoring a wearable biological sensor

A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.

Large capacity solid state battery

Aspects of the present disclosure relate to a method for fabricating an interconnection layer carrying structure. A carrier is provided. An organic layer is deposited on the carrier, wherein the organic layer includes a multi-layer wiring structure therein, and the uppermost surface is covered with an organic top layer. A sacrificial layer is deposited on the organic top layer. The carrier and the organic layer are diced together with the sacrificial layer.

Fabricating an interconnection using a sacrificial layer

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher. The surface treatment includes sandblasting.

Prevention of bridging between solder joints

An interconnection structure is disclosed. The interconnection structure includes a base substrate, a set of conductive pads disposed on the base substrate and an interconnection layer disposed on the base substrate. The interconnection layer has an edge located next to the set of the conductive pads and includes a set of side connection pads located and disposed at the edge of the interconnection layer. Each side connection pad is arranged with respect to a corresponding one of the conductive pads disposed on the base substrate.

Interconnection with side connection to substrate

A method of fabricating a connection structure is disclosed. The method includes providing a substrate that has a top surface and includes a set of pads for soldering, each of which has a pad surface exposed from the top surface of the substrate. The method also includes applying a surface treatment to a part of the top surface of the substrate close to the pads and the pad surface of each pad so as to make at least the part of the top surface and the pad surfaces of the pads rougher.

A semiconductor device includes a semiconductor chip having a first main surface, a second main surface opposite to the first main surface, a side surface arranged between the first main surface and the second main surface, and a magnetic storage device, a first magnetic shield overlaying on the first main surface, a second magnetic shield overlaying on the second main surface, and a third magnetic shield overlaying on the side surface. The first and second magnetic shields are mechanically connected via the third magnetic shield.

Semiconductor device including a plurality of magnetic shields

A yield of semiconductor devices having a magnetic shield is enhanced. A magnetic shield member SIE has a first shield member SIEand a second shield member SIE. The first shield member SIEhas a first facing region FPfacing a first surface of a semiconductor chip SC. The second shield member SIEhas a second facing region FPfacing a second surface of the semiconductor chip SC. A resin layer RLhas a portion thereof making contact with the first shield member SIE, and has another portion thereof making contact with the second shield member SIE. Then, the first shield member SIEand the second shield member SIEare magnetically coupled via the resin layer RLor directly. The first shield member SIEand the second shield member SIEcover a magnetic memory cell MR in plan view.

Semiconductor device

A semiconductor chip includes a magnetic storage device and includes an electrode pad on a first face. The semiconductor chip is coated with a magnetic shield layer in a state in which at least the electrode pad is exposed. The semiconductor chip is mounted on an interconnect substrate through a bump. At least one of the semiconductor chip and the interconnect substrate includes a convex portion, and the bump is disposed over the convex portion.

Growing community of inventors

Kanagawa, Japan

Takahito Watanabe