Toshiba Memory Corporation

Kioxia Corporation

Takahito Nishimura

Yoshihisa Kawamura

Takamasa Usui

Ikuo Yoneda

Masayoshi Tagami

Jun Iijima

Kazuhiro Takahata

Yoshiharu Ono

Takuya Nishikawa

Suigen Kanda

Sota Matsumoto

Satoshi Usui

Yoshihiro Yanai

Genki Kawaguchi

Kiminori Yoshino

Hironobu Tamura

Yusuke Okumura

Kazuyuki Yoshimochi

Sonoe Matsushita

Jun Iljima

According to one embodiment, a semiconductor memory device includes: a first stacked body that includes a memory region, a stepped region, and a connection region arranged in a first direction; a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction; a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region in the stacking direction; and a plurality of third pillars that extends in the first stacked body in the stacking direction, and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.

Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars

According to one embodiment, a semiconductor memory device includes: a stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and a stepped portion in which the plurality of conductive layers is processed in a stepped shape; and a plurality of second pillars that extends in the stacked body in the stepped portion, in which each of the plurality of second pillars includes a second insulating layer extending in the stacked body in the stacking direction, a semiconductor layer covering a side wall of the second insulating layer, a third insulating layer disposed in contact with a side wall of the semiconductor layer and covering the side wall of the semiconductor layer, and a fourth insulating layer disposed in contact with a side wall of the third insulating layer and covering the side wall of the third insulating layer.

Semiconductor memory device

A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory region in which a plurality of memory cells are disposed and a staircase region in which end portions of the plurality of conductive layers form a staircase shape. A first region of the staircase region includes a first sub-staircase portion ascending in a first direction toward the memory portion, and a second sub-staircase portion disposed side by side with the first sub-staircase portion in a second direction opposite to the first direction from the first sub-staircase portion and ascending in the second direction.

Semiconductor storage device comprising staircase portion

According to one embodiment, a semiconductor memory device includes a substrate, insulating members, first conductive layers, first pillars, and second pillars. The substrate includes a first area, a second area, block regions, and a first dummy block region. The insulating members are arranged at respective boundary portions of the block regions and the first dummy block region. The first conductive layers are partitioned by the insulating members. The first pillars penetrates the first conductive layers in a region where the first area and the block regions overlap. The second pillars penetrates at least one of the first conductive layers in a region where the first area and the first dummy block region overlap.

A semiconductor storage device according to an embodiment includes: a stacked body in which a plurality of conductive layers are stacked via an insulating layer and which has a memory portion in which a plurality of memory cells are disposed and a staircase portion in which end portions of the plurality of conductive layers form a staircase shape. The staircase portion has three or more first sub-staircase portions ascending in a direction opposite to a direction toward the memory portion, and at least one first sub-staircase portion among the three or more first sub-staircase portions is divided into at least an upper staircase and a lower staircase by a difference in level larger than a difference in level of each stair of the first sub-staircase portion.

Semiconductor storage device comprising staircase portion and method for manufacturing the same

A semiconductor storage device according to one embodiment is the semiconductor storage device that includes: a cell array region having a plurality of memory cells; and an outer edge portion arranged at an end portion to surround the cell array region. A stacked body in which a plurality of conductive layers are stacked via a first insulating layer and which has a stair portion in which end portions of the plurality of conductive layers form a stair shape is provided inside the cell array region, the stair portion facing the outer edge portion. A center of at least one step of the stair portion has a recess directed to an inner side of the cell array region.

Semiconductor storage device and method for manufacturing semiconductor storage device

An imprinting system according to an embodiment includes a first measuring device measuring an intensity of light reflected from an end of a shot area of a monitor substrate being an area on which imprinting has been performed, a dripping condition generating device generating a dripping condition of a resin-based mask material on the basis of the measured intensity of light, and an imprinting apparatus performing imprinting using the dripping condition. The imprinting apparatus includes a second measuring device measuring an intensity of light reflected from an end of a first shot area of a production substrate being an area on which imprinting has been performed, and a control unit adjusting arrangement of droplets of a resin-based mask material ejected on a second shot area of the production substrate being an area on which imprinting is to be performed on the basis of an intensity of light reflected from an end of the first shot area.

Imprinting system, method of manufacturing semiconductor device, and recording medium

According to an embodiment, a template includes a flat plate-shaped first member, a flat plate-shaped second member including a pattern arrangement face, and a flat plate-shaped third member provided with an opening at a position corresponding to an arrangement position of the second member. The template is dividable at a position of at least one of a first boundary between the first member and the second member and a second boundary between the first member and the third member.

Template, template component, and semiconductor device manufacturing method

According to an embodiment, a semiconductor memory device includes a substrate, a stacked body, a plurality of columnar portions, a plurality of interconnects, and a plurality of connection portions. The plurality of interconnects extends in a first direction parallel to an upper surface of the substrate. When viewed from a second direction perpendicular to the stacking direction and the first direction, a portion of a first connection portion overlaps a portion of a second connection portion. The first connection portion is connected to a first interconnect of the plurality of interconnects. The second connection portion is connected to a second interconnect of the plurality of interconnects adjacent to the first interconnect in the second direction.

Staggered semiconductor memory device

According to one embodiment, an imprinting apparatus is provided. The imprinting apparatus includes a controller that controls a resist drop position on a wafer to be imprinted with a pattern, using a first resist drop recipe corresponding to a first topography of the wafer.

Imprinting apparatus, recording medium, and imprinting method

According to one embodiment, a device substrate includes a multilayer film that includes a film constituting a device element and is disposed on a substrate. A main face on which the device element is disposed includes a patterning region on which a resist is to be applied during an imprint process, and a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device substrate. The bevel region includes a region where an upper surface of the bevel region becomes lower toward the end portion of the device substrate relative to an upper surface of the patterning region. The upper surface of the bevel region has an inclination angle of 10&#xb0; or more and 90&#xb0; or less with respect to the upper surface of the patterning region, at a boundary between the patterning region and the bevel region.

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Kuwana, Japan

Takahito Nishimura