Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Mitsubishi Denki Kabushiki Kasiha

Takahisa Eimori

Shinichi Satoh

Hiroji Ozaki

Yoshinori Tanaka

Wataru Wakamiya

Hiroshi Kimura

Toshiyuki Oashi

Nobuyuki Mise

Natsuo Ajika

Hideaki Arima

Tadashi Nishimura

Hirofumi Shinohara

Kiyoto Watabe

Kenichi Shimomura

Jiro Matsufusa

Yasushi Hashizume

Yuichi Nakashima

A CMOS semiconductor device having an n-type MOSFET and a p-type MOSFET, comprising: a gate electrode of the n-type MOSFET having a first insulation layer composed of a high-k material, and a first metal layer provided on the first insulation layer and composed of a metal material; and a gate electrode of the p-type MOSFET having a second insulation layer composed of a high-k material, and a second metal layer provided on the second insulation layer and composed of a metal material, wherein the first insulation layer and the second insulation layer are composed of the different high-k materials, and the first metal layer and the second metal layer are composed of the same metal material.

CMOS semiconductor device and method for manufacturing the same

A base insulating film containing hafnium and oxygen is formed on a silicon oxide (SiO) film formed on a main surface of a substrate. Subsequently, a metal thin film thinner than the base insulating film and made of only a metal element is formed on the base insulating film, and a protective film having humidity resistance and oxidation resistance is formed on the metal thin film. Then, by diffusing the entire metal element of the metal thin film into the base insulating film in a state of having the protective film, a mixed film (high dielectric constant film) thicker than the silicon oxide film and having a higher dielectric constant than silicon oxide and containing hafnium and oxygen of the base insulating film and the metal element of the metal thin film is formed on the silicon oxide film.

Method of manufacturing semiconductor device and semiconductor device

A lower portion of an interlayer insulating film is formed contiguous with a semiconductor wafer. The lower portion has a high impurity concentration and a high etching rate. An upper portion of an interlayer insulating film is formed over the lower portion apart from the semiconductor wafer. The upper portion has a low impurity concentration and a low etching rate. A plurality of contact holes are formed through the interlayer insulating film by anisotropic etching. The bottom portion of each contact hole is expanded by isotropic etching, and a contact is formed in the contact hole. Thus, a satisfactory contact is formed in a hole of a large aspect ratio.

Semiconductor device with multiple layer insulating film

Semiconductor device and method of fabricating the same

A transfer mark structure for a multi-layer interconnecting process for avoiding the influence of dishing when a groove pattern for multi-layer interconnection is formed, and for improving the accuracy and stability of reading the transfer mark used for transfer in the following step so as to align with a location of transfer in the preceding step, and a method for producing such a transfer mark for the multi-layer interconnecting process. The underlying layer immediately under the transfer mark for photoengraving formed in the step of connecting between interconnecting layers has a groove-like pattern.

Transfer mark structure for multi-layer interconnecting and method for the manufacture thereof

In a peripheral circuit region requiring a conductive path between layers at the periphery of a memory cell array region, a conductive path is provided, after removing a silicon nitride film used for self-alignment contact from the area of the contacting portion of a conductor, by forming an interlayer oxide film on the conductor and providing an opening through the interlayer oxide film. Alternatively, a conductive path is provided, after forming the interlayer oxide film on the silicon nitride film used for self-alignment contact, by forming an opening throughout the interlayer oxide film and silicon nitride film.

Semiconductor device and manufacturing process thereof

Semiconductor device having self-aligned contacts

A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.

Method for forming MOS device having field shield isolation

In a dynamic semiconductor memory device including a thin film SOI/MOSFET having a semiconductor layer on an insulator as an active region, an 'L' level potential of a memory cell transistor, which connects/disconnects a capacitor for storing data as electric charges and a bit line for reading/writing data, is set at a fixed value higher than a ground potential and lower than a power supply potential, and a substrate bias is set at the ground potential. Even if isolation is carried out by LOCOS, sub-threshold leakage current due to a parasitic MOS in the vicinity of LOCOS edge can be suppressed because the potential of a word line is lower than that of the bit line when the memory cell transistor is in a cut-off state. Therefore, a dynamic semiconductor memory device including a thin film SOI/MOSFET which is immune to disturbing refresh can be achieved.

Dynamic semiconductor memory device on SOI substrate

A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.multidot.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Field effect transistor with a shaped gate electrode

A buried insulating layer is provided in a semiconductor substrate, in a position separated from its major surface. A LOCOS isolation film is provided in the major surface of the semiconductor substrate for isolating an active region from other active regions. A thin-film transistor is provided in the active region. The thin-film transistor comprises a gate electrode which is provided on the active region with interposition of a gate insulating layer. A pair of source/drain layers are provided in the major surface of the semiconductor substrate on both sides of the gate electrode. A high-concentration impurity layer is provided in the semiconductor substrate immediately under the buried insulating layer.

Thin-film transistor having a buried impurity region and method of

In a semiconductor memory device, pitch of bit lines is made larger than pitch of word lines, and a storage node contact is positioned in each rectangular area surrounded by the bit lines and the word lines. The distance between centers of adjacent storage node contacts and the distance between centers of a bit line contact and an adjacent storage node contact are both made larger than the pitch of word lines. By this structure, planar area per unit memory cell can be increased, registration margin between the storage node and the storage node contact can be enlarged, short-circuit between the bit line and the storage node contact is prevented, and thus a memory cell structure of high production yield and high reliability can be realized.

Semiconductor memory device

A semiconductor device having an SOI structure which involves no parasitic MOS transistor and substrate floating effect and has a planar element isolation region and, a manufacturing method therefor. In the semiconductor device, a field shield gate composed of an oxide film and a field shield gate electrode is formed to be buried under an SOI layer. As a result, it is possible to prevent generation of a parasitic transistor and substrate floating effects inherent in field shield gate while obtaining a planar element isolation structure.

Semiconductor device having SOI structure and manufacturing method

A field effect transistor comprises a semiconductor substrate having a main surface and a predetermined impurity concentration of a first conductivity type, impurity layers of a second conductivity type formed spaced apart at the main surface of the semiconductor substrate, and a shaped conductive layer serving as a gate electrode. The impurity layers constitute source.drain regions, and a region between the impurity layers defines a channel region in the main surface. The shaped conductive layer is formed on the channel region with an insulating film therebetween. The shaped conductive layer has an upper portion and a lower portion wherein the upper portion is longer than the lower portion and the length of the lower portion adjacent the insulating film is substantially equal to or shorter than the length of the channel region at the main surface. Additionally, the upper and lower portions of the shaped conductive layer are formed of the same base composition.

Method of making a field effect transistor with a T shaped polysilicon

An SOI-MOS transistor structure is obtained which enables prevention of a substrate floating effect, reduction of the gate capacity and the contact resistance, and connection of two or more transistors in series. A semiconductor device including this transistor includes a pair of n.sup.+ type source/drain regions and a p.sup.+ type channel potential fixing region formed by dividing an active region by a first wiring and a second wiring, and a third wiring and a fourth wiring extending from respective side portions of the wirings. Since holes stored in an effective channel region flow in the p.sup.+ type channel potential fixing region, the substrate flowing effect can be prevented. Since one region of the pair of n.sup.+ type source/drain regions is wider than the other region, the contact resistance can be decreased. Further, since the gate wirings are not connected to each other, transistors can be connected in series.

Growing community of inventors

Hyogo, Japan

Takahisa Eimori