Kabushiki Kaisha Toshiba

Matsushita Electric Industrial Co., Ltd.

Semiconductor Technology Academic Research Center

Honda Motor Co., Ltd.

Rio Co., Ltd.

Takahiro Yamashita

Koichiro Ishibashi

Yukio Arima

Fumihiko Tachibana

Shuhei Kondo

A vehicle body transport system includes an unmanned carrier carrying and transporting a vehicle body between work stations; and an imaging device including an imaging part imaging a traveling route of the unmanned carrier and the surroundings of the traveling route from above, an analysis part analyzing an image captured by the imaging part, and a transmission part transmitting a signal to the unmanned carrier. When a moving object other than the unmanned carrier carrying the vehicle body is present in the image, the analysis part predicts whether a movement trajectory that the vehicle body passes after a predetermined time intersects a movement position where the moving object is located after the predetermined time. When predicting that the movement trajectory and the movement position intersect after the predetermined time, the transmission part transmits an emergency operation signal to the unmanned carrier before the predetermined time elapses.

Vehicle body transport system

A semiconductor integrated circuit device according to an embodiment includes at least one first transistor connected at its source to an input power supply line, connected at its drain to an output power supply line, and connected at its gate to a first control line, at least one second transistor connected at its source to the input power supply line, connected at its drain to the output power supply line, and connected at its gate to a second control line, a first buffer which drives the first control line, a second buffer configured to receive a control signal input via the first control line and drive the second control line, and a plurality of transfer gates provided to divide the first control line into a plurality of pieces, the plurality of transfer gates being capable of connecting pieces obtained by dividing the first control line.

Semiconductor integrated circuit power supply control device

In the device, a pair of transistors includes first and second transistors connected in parallel between a power-supply-line and a power-supply or between a ground-line and a ground-potential. A third transistor is connected between the power-supply-line and the power-supply or between the ground-line and the ground-potential. First to third nodes are gate nodes of the first to third transistors. A first buffer outputs a first control-signal for controlling the first transistor. A second buffer is connected between the first node and the second and third nodes to receive the first control-signal and transmit a second control-signal for controlling the second and third transistors to the second and third nodes in parallel. When power-supplying starts, the second control signal drives the second and third transistors to the conductive-state after the first control-signal controls the first transistor to be driven in an intermediate-state between the conductive-state and a shutoff-state.

Semiconductor integrated circuit device having power enable lines transferring control signals

According to one embodiment, a semiconductor memory device includes first to fifth units. The first unit compares first data being write target data before write in a memory, with second data written in the memory and then read out. The second unit stores the first data if a data comparison result indicates mismatch. The third unit stores a write address corresponding to the write target data if the data comparison result indicates mismatch. The fourth unit compares a read address corresponding to read target data with an address stored in the third unit. The fifth unit selects data read out from the memory in accordance with the read address as the read target data if a address comparison result indicates mismatch, and selects data read out from the second unit as the read target data if the address comparison result indicates match.

Semiconductor memory device detecting error

A safety confirmation system includes a mobile terminal that receives early disaster information, a center apparatus that manages a safety status of a user of the mobile terminal, and a map server that provides map information. The mobile terminal holds destination information and automatically acquires current location information upon receiving the early disaster information. The mobile terminal automatically transmits the current location information to the center apparatus and the map server, and automatically transmits the destination information to the map server. The center apparatus receives the current location information transmitted from the mobile terminal. The map server searches for a return route from the current location to a destination, generates map information including the return route, and transmits the map information to the mobile terminal. The mobile terminal receives and stores the map information including the return route and displays the map information.

Safety confirmation system, mobile terminal for use in safety confirmation system, and safety confirmation method

A semiconductor integrated circuit comprises: a first signal delay circuit including a first precharge element configured to precharge a first node with a leakage current and a first signal output circuit configured to output a first signal; a second signal delay circuit including a second precharge element configured to precharge a second node with a leakage current and a second signal output circuit configured to output a second signal. The first signal delay circuit is configured to discharge the first node via a first discharge element, while the second signal delay circuit precharges the second node via the second precharge element and outputs the second signal. The second signal delay circuit is configured to discharge the second node via a second discharge element, while the first signal delay circuit precharges the first node via the first precharge element and outputs the first signal.

Semiconductor integrated circuit

A semiconductor integrated circuit deviceincludes a plurality of basic cellseach having therein a logic transistorthat performs logical operations, and a power switching transistorthat can interrupt leakage current when the logic transistoris not operated. The semiconductor integrated circuit devicefurther includes a wiringthat connects virtual power nodesas the connection points between the logic transistorsand the power switching transistors, between individual basic cellsandincluded in a plurality of basic cells. Here, a basic cell includes a power switching transistorsthat can interrupt leakage current when the logic transistorsare not operated, in addition to the logic transistors. Thereby, switching transistorscan be disposed in the optimal positions of the cells, and basic cellshaving a small restriction in disposition and wide scope of application can be provided.

Semiconductor integrated circuit device

A first output transistor forms a first current path between an input and an output terminal and has a first control terminal applied with a first control signal. A second output transistor forms a second current path between the output and a ground terminal and has a second control terminal applied with a second control signal. A first comparator outputs the first control signal to decrease an ON-resistance of the first transistor when an output voltage from the output terminal is a predetermined value or less. A second comparator outputs the second control signal to render the second transistor conductive to decrease the output voltage when the output voltage is a predetermined value or more. An acceleration circuit accelerates charging of the first control terminal of the first transistor to a predetermined potential. The inhibition circuit inhibits the acceleration circuit operation according to a change of the second control signal.

Constant voltage power supply circuit

A semiconductor integrated circuit device, has a semiconductor substrate; and a first transistor of a first conductivity type and a second transistor of the first conductivity type, the transistors being connected in series between a first power supply line and a first substrate well provided on the semiconductor substrate, the semiconductor integrated circuit device further comprising a first transistor of a second conductivity type and a second transistor of the second conductivity type, the transistors being connected in series between the second power supply line and a second substrate well provided on the semiconductor substrate.

An integrated circuit device includes at least one functional module which outputs save data in synchronism with a saving clock signal, a power supply control unit which selects one of the functional modules, and controls stop and resumption of power supply to the selected functional module, a save data storage unit which stores save data output from a functional module selected by the power supply control unit, and an error checking and correction unit which performs error checking and correction for the save data stored in the save data storage unit when the save data is to be restored to the functional module in synchronism with a restoration clock signal.

Power management for circuits with inactive state data save and restore scan chain

A data retaining circuit has been disclosed in which, even if a soft error occurs, it is corrected and a normal value can be maintained, the configuration is simple, and high-speed operations are enabled. In this circuit, when a soft error occurs in the data to be put out, it is corrected by a pull-up path or a pull-down path, and when a soft error occurs in the data in the pull-up path or the pull-down path, the error data in the pull-up path or the pull-down path is prevented from affecting each other, as well as turning off the correcting function to prevent the influence on the data to be put out.

Data retaining circuit

A semiconductor integrated circuit device has a MISFET and a body biasing circuit. The MISFET has a source electrode and a drain electrode of a first conductivity type and a gate electrode, and the MISFET is formed in a well of a second conductivity type. The body biasing circuit generates a voltage in the well by passing a prescribed current in a forward direction into a diode which is formed from the well and the source electrode of the MISFET.

Semiconductor integrated circuit device having body biasing circuit for generating forward well bias voltage of suitable level by using simple circuitry

Growing community of inventors

Tokyo, Japan

Takahiro Yamashita