Nec Corporation

Other

Nec Informatec Systems, Ltd.

Takahiro Yaguchi

Takashi Harada

Seishi Eya

Hideki Sasaki

Osamu Matsuda

Akira Wakui

Toshihide Kuriyama

Kiyoshi Asao

Yoshiaki Maruyama

Shunsuke Fujimoto

A power integrity analyzer according to an exemplary aspect of the invention includes a parameter inputting unit that inputs parameters to a power-supply current waveform which indicates a variation of a power-supply current value on a time axis of an element, a conversion unit that converts the power-supply current waveform which indicates a variation on the time axis determined by the parameter to a power-supply current spectrum which indicates a variation of the power-supply current value on a frequency axis, an allowable value information storage unit that stores an allowable power-supply voltage fluctuation value of the element, and an impedance calculating unit that calculates a target impedance spectrum on the device indicating the variation of impedance value on the frequency axis based on the power-supply current spectrum and the allowable power-supply voltage fluctuation value.

Power integrity analyzer, power integrity analysis method, and program

A design rule check system includes: a design rule check unit that performs a design rule checks on wiring information which indicates a wiring pattern of a net on the basis of a design rule which includes a constraint condition of a wiring pattern; and a screening processing unit which generates information about an error for each clock frequency of each net based on a result of the design rule check and outputs the information to an indicating device.

Rule check system, design rule check method and design rule check program

To estimate the number of layers required for drawing wirings out of a BGA component at a high speed. A layer number estimation device includes: a bottleneck line detection means, a wiring layer adding means, and a repeating means. The bottleneck line detection means detects a line as a bottleneck line, among a plurality of lines formed by connecting electrodes, where the number of electrodes located nearer the center side than the lines is greater comparing with the number of wirings capable of passing through the lines. The wiring layer adding means disposes electrodes, among the electrodes located nearer the center side than the bottleneck line, which remain after subtracting the number of wirings capable of passing through the bottleneck line, on the next wiring layer with vias. The repeating means causes the bottleneck line detection means and the wiring layer adding means to be executed to the next wiring layer.

Device, method and program for estimating the number of layers BGA component mounting substrate

A device for estimating the required number of board layer to provide necessary wiring in a printed circuit board or a LSI package, a system including the device, a method and a program for estimating the same. In this system, positional information of pins mounted to each component and a board, and connection information between pins are retrieved from a pin positional information file and a net list file. Further, information about an order of layers to be added, a diameter of a via in respective layers and obstacles to wiring is retrieved from the net list file an added layer structure defining file. Thereafter, information about a layer structure, vias, an area where wiring is prohibited is stored in a storage. A wiring route searching section determines whether or not it is possible to form necessary wiring under the present structure. When the wiring route searching section determines it to be impossible, a layer in the next order is added according to information about added layers. Subsequently, the wiring route searching section judges the possibility again. When determining it to be possible, the wiring route searching section outputs the present layer structure to an output device. By this means, it becomes possible to estimate a layer structure and the number of layers.

Device for estimating number of board layers constituting board, system including the device, and method for estimating the same and program for executing the method

A printed circuit wiring board designing support device includes a layout data receiving section receiving printed circuit board layout data through an input/output section, a section for extracting structures of power supply/ground planes, a via hole extracting section for extracting a via hole interconnecting the wirings extending over power supply/ground planes, a capacitor extracting section for extracting a capacitor connected between power supply/ground planes, a distance measuring section for measuring the distance between the via hole and the capacitor, a database where the allowable distance value between the via hole and the capacitor in respect to the distance between the power supply and ground planes is recorded, an examination section for comparing the capacitor/via hole distance with the allowable distance value, and a warning section for issuing a warning when the distance between the via hole and the capacitor is larger than the allowable distance value.

Printed circuit wiring board designing support device, printed circuit board designing method, and its program

There is provided a circuit design supporting device, a circuit board design supporting system, a circuit board design supporting server, a circuit board design supporting client, a circuit design supporting method, and a program for realizing the device for designing a layout of main components such as LSI, etc. on a circuit board such as a printed circuit board wherein unnecessary electromagnetic radiation is suppressed. The circuit design supporting device comprises a noise generating level adding means and a component locating means. The noise generating level adding means adds noise generating level information to a component to be located on a printed circuit board. The component locating means includes a component position detecting section, a voltage distribution detecting section, a noise generating level comparing section, and an error informing section. The component position detecting section detects a position of the component moved on the printed circuit board. The voltage distribution detecting section detects a voltage level on the printed circuit board in the detected position of the component. The noise generating level comparing section compares the detected voltage level with the noise generating level added to the component. The error informing section informs a user of an error when the voltage level on the printed circuit board is equal to or larger than the noise generating level as a result of the comparison.

Device, system, server, client, and method for supporting component layout design on circuit board, and program for implementing the device

In a printed circuit board design support apparatus for supporting design of a printed circuit board by calculating a radiation amount of electromagnetic radiation caused by an interconnection on the basis of design information related to each of the printed circuit board having a ground plane, interconnections formed on the printed circuit board, and components to be mounted on the printed circuit board, an arithmetic unit calculates a common mode (CM) radiation amount of the interconnection on the basis of a CM radiation amount ratio that indicates a ratio of a common mode (CM) radiation amount of electromagnetic radiation caused by the ground plane in correspondence with the interconnection to a differential mode (DM) radiation amount of electromagnetic radiation caused by the interconnection. A printed circuit board design support method and program are also disclosed.

Printed circuit board design support apparatus, method, and program

Disclosed is a power decoupling circuit generating system and method capable of easily generating a power decoupling circuit for each device such as an LSI. On the basis of information regarding parameters of generating a power decoupling circuit held in a capacitor parts library and a line calculation parameter file, a power decoupling circuit of a &pgr;-type low pass filter construction having first and second decoupling capacitors to be added to a power supply terminal of a device as a target from which high frequency noise is prevented from being passed to a power plane and a power line corresponding to an inductance is automatically generated by a power decoupling circuit generating unit, thereby making calculation for generating the power decoupling circuit unnecessary.

Power decoupling circuit generating system and power decoupling circuit generating method

An incandescent lamp which is operable at about 200-275 V is obtainable by enclosing a filling composition consisting of about 80-95% by volume of krypton gas and about 5-20% by volume of nitrogen gas in a glass envelope bearing a tungsten filament and an inner volume of about 0.2-1.2 ml/operating wattage in an amount of about 0.7-0.9 ml/ml of the inner volume. The incandescent lamp exhibits satisfactory luminous characteristics and an extended life expectancy without causing arc discharge even when operated at a voltage of about 200-275 V. Thus a lighting device which comprises such an incandescent lamp as the luminous source and a power source capable of energizing it at a voltage of about 200-275 V is very useful in general and special illumination.

High voltage incandescent lamp with low-pressure Kr/N.sub.2 gas fill

A filling composition consisting essentially of about 20-75% by volume of xenon gas and about 15-80% by volume of nitrogen gas exhibits excellent luminous characteristics and an extended life expectancy but hardly causes arc discharge when enclosed in incandescent lamp. Incandescent lamps using the filling composition emit a light which is natural, appropriately high in color temperature, excellent in color rendering properties and gentle to the eye when operated at a voltage exceeding their rating but not exceeding 150% thereof.

Growing community of inventors

Tokyo, Japan

Takahiro Yaguchi