Kabushiki Kaisha Toshiba

Takahiro Tokuyoshi

Ken Tanabe

A debugging support device includes: a plurality of CPU simulating units which simulates the operations of a plurality of CPUs which executes programs in parallel; a memory simulating unit of a memory to be shared by the plurality of CPUs; an event monitoring unit that detects a predetermined event occurring between each CPU simulating unit and the memory simulating unit; and a state judging unit that judges whether the state of the occurred predetermined event matches a predetermined condition and, if the predetermined condition is matched, records history information related to the state of the memory simulating unit.

Debugging support device, debugging support method, and program thereof

The present invention has the following arrangement. That is, an instruction stream for performing an instruction simulation is analyzed before the instruction simulation is started to predict a timing at which interruption occurs, an interrupt generating unit generates a predictive interrupt signal one instruction cycle before interruption occurs on the basis of the prediction result, and, when an instruction which is executed immediately after the predictive interrupt signal is generated has a flag-less instruction identifier, an execution process of the instruction which is executed immediately after the predictive interrupt signal is generated is performed according to not a flag-less instruction code but a flag instruction code.

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Kanagawa, Japan

Takahiro Tokuyoshi