Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Electric Semiconductor Software Co., Ltd

Mitsubishi Electric Semiconductor Software Corporation

Other

Takahiro Tani

Yukiharu Mikawa

Tadateru Kamimizo

An MWL signal encoding part encodes a signal occurring on a main word signal line, an SD signal encoding part encodes a signal occurring on a subdecode signal line, a WL calculating part calculates a WL value, based on an MWL signal encoded value and an SD signal encoded value; an input and output operation part allows one-word data in a memory cell selected by the WL value to be read and written via the bit signal line; and a read and write control part controls a read operation and a write operation of the input and output operation part, based on a signal level on the bit signal line.

Logic simulation method and logic simulation apparatus

A fault simulation apparatus includes an MOS transistor output signal strength determining portion for extracting the conductivity type of an MOS transistor in which an event such as a variation in signal level occurs. A control signal value is obtained from a control terminal, and an input signal value is obtained from an input terminal, and output signal strength when the event occurring MOS transistor is turned ON is determined. In the apparatus, fault simulation is performed depending upon the output signal strength determined by the output signal strength determining portion.

Fault simulation apparatus

A semiconductor circuit logical check apparatus including a unit for extracting information about laser trimming fuse elements based on layout data and logic-circuit diagram data of a semiconductor circuit, a unit for generating a command sequence indicating that some of the laser trimming fuse elements are broken on the basis of the extracted laser trimming fuse element information, a unit for generating error bit memory cell array models from memory cell array models, and a unit for executing, on a semiconductor circuit model, logic simulation on the basis of the command sequence.

Logical check apparatus and method for semiconductor circuits and

A logic simulation device includes an indefinite value generating signal line extracting unit, a propagation deciding unit and a message output unit. The logic simulation device is supplied with circuit connection data of a logic circuit and input signal data employed for simulating the logic circuit. The indefinite value generating signal line extracting unit extracts a signal line which enters a floating state in excess of an allowance time or that causes a collision of logic states as an indefinite value generating signal line. The propagation deciding unit decides whether or not a propagation candidate gate having a propagation input end which is connected with an indefinite value generating signal line is in a state propagating the indefinite value to its output. The propagation deciding unit decides that the indefinite value generating signal line is an error signal line causing an error only when the propagation candidate gate is in a state of propagating the value at the propagation input end. The message output unit outputs a warning message for indicating that the error signal line is a signal line to which the indefinite value generated by an operation of the circuit may be propagated to feed a through current.

Logic simulator and logic simulation method

In a switch level simulation system of the present invention, bidirectional switch models are allocated more accurately at locations which need to be bidirectional in circuit connection information and uni-directional switch models corresponding to the flow direction of a signal are allocated at the other locations. The connection information extracting section extracts the connection state of each device in a circuit indicated by circuit information and produces connection information. The input/output type determining section determines whether or not a switching device in a circuit is bidirectional and the flow direction of a signal in a uni-directional switching device, according to connection information. The circuit connection information generating section generates circuit connection information to be used by a simulation executing section, using the result of determining of the input/output type determining section.

Switch level simulation system

The temperature of the circuit to be verified is evaluated. A simulation executing section (101) executes logic simulation of the circuit to be verified expressed in function block units at function block level. A circuit action extracting section (103) extracts an actin mode of a function block in its process. A total current consumption calculating section (105) calculates the total current consumption which is the current consumed in the entire circuit to be verified, on the basis of the data of current consumption in each action mode and extracted action mode. An average current calculating section (107) calculates the average current which is the average of the total current consumption over the check period, reflecting the thermal characteristic of the circuit to be verified. An allowable temperature judging section (109) calculates the temperature of the circuit to be verified according to this average current, and compares with an allowable current. An error message output section (110) issues a message when the temperature exceeds the allowable temperature. The temperature can be evaluated, therefore, by using logic simulation. (FIG. 1)

Simulation apparatus for circuit verification

There are provided a logic simulator apparatus and a circuit simulation apparatus capable of simulation based on signal propagation delay time with high reliability. A voltage drop calculating portion (9) calculates a voltage drop value (Vi) on the basis of power-supply information (D4), drain current (Ii) and voltage drop resistance (Ri). A propagation delay calculating portion (10) calculates delay time (Di) required for each element to propagate a logic signal value on the basis of gain coefficient (.beta.i), interconnection parasitic capacitance (Cj) and voltage drop value (Vi). A logic simulation performing portion (12) performs the logic simulation on the basis of the circuit connection data (D22) provided with the delay time (Di). Accordingly, logic and circuit simulation can be accomplished on the basis of the signal propagation delay time with high reliability.

Logic simulation apparatus and circuit simulation apparatus

A timing simulation system has a layout pattern data storage portion, a data extracting portion, a process parameter storage portion, a gain coefficient calculating portion, an attendant capacitance supply portion, and a timing simulation executing portion. The gain coefficient calculating portion and the attendant capacitance calculating portion calculate gain coefficients and attendant capacitances peculiar to elements and wires from the circuit connection data extracted from layout pattern data of a logic circuit, and the gain coefficient supply portion and the attendant capacitance supply portion set the gain coefficients and the attendant capacitances. The timing simulation executing portion calculates the total load capacitance and the total gain coefficient with respect to a group of equipotential wires in which the signal value changes, calculates the transition time of the signal value on the wires based on the total load capacitance and the total gain coefficient, and executes timing simulation while using the transition time as a signal propagation delay time.

System for simulating electrical delay characteristics of logic circuits

A MOST output signal determiner (4) with output signal strength verifying function receives a circuit connection data (D4) with MOS input information to determine the signal strength of an output signal which appears at an output terminal (drain or source) of an MOS transistor as a function of an input signal. A logic simulator verifies circuit operating characteristics in consideration for signal transmitting characteristics on the input signal of the MOST, the presence/absence of a through current in the MOST and an accurate state transition delay time through the MOST.

Logic circuit simulator for verifying circuit operations having MOS

In the inventive layout pattern verification system, verification data employed by a verification data judging part for judging effectiveness/defectiveness of the electrical property of a logic circuit formed by a layout pattern are data calculated by a verification data calculation part on the basis of reference circuit constants extracted from layout pattern data by a second data extraction part and process parameters supplied by a process parameter supply part, i.e., data obtained with no circuit simulation. Thus, the electrical property of the layout pattern of a large-scale logic circuit can also be easily verified by judging effectiveness/defectiveness of the electrical property of the logic circuit formed by a layout pattern through a verification data judging part on the basis of the verification data.

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Hyogo, Japan

Takahiro Tani