Other

Hitachi, Ltd.

Hitachi Ulsi Engineering Corp.

Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Takahiro Sonoda

Sadayuki Morita

Takeshi Sakata

Osamu Nagashima

Haruko Tadokoro

Hideharu Yahata

Kenichi Fukui

Tomohiro Nagano

Hirofumi Zushi

Haruko Kawachino

Masashige Harada

Yoji Nishio

Satoru Hanzawa

Atsushi Hiraishi

Hiroshi Toyoshima

Kunihiro Komiyaji

Hiroshi Ichikawa

Yoshinobu Nakagome

Yoshikazu Saitoh

Toshiaki Kashihara

Shinichi Ito

Shigeki Maekawa

Hiroya Ikuta

Shinji Iwamoto

Hideyuki Kanuka

Gaku Saitou

Shigeharu Nagai

Yoichi Nakai

Efficient generation of test scenarios without excess or lack thereof can be supported. A test scenario generation support device includes a storage device which holds use case scenarios relating to an application of a test target and a computation device which identifies from the use case scenarios a vocabulary on a screen display using a predetermined rule, identifies a screen object corresponding to the identified vocabulary for each of the use case scenarios using a predetermined algorithm, and generates a test scenario based on a test pattern defined in advance for each screen object.

Test scenario generation support device and test scenario generation support method

An objective is to provide a pressure-contact type rectifier in which solder that increases the environmental load is not used, and neither burning nor breakage of a rectifying device occurs, even if temperature of the rectifying device increases due to current flowing or force towards outside the rectifying device is applied to a lead end, etc. By providing an electrically conductive friction reducer on at least one electrode face of the rectifying device, the temperature increase can be prevented, and the friction at the contact face can be reduced. Moreover, by providing a flexible portion on the lead end outside a cap, and fixing the flexible portion to the cap, the contact area between the lead and the rectifying device can be kept constant. As a result, a pressure-contact type rectifier in which neither burning nor breakage of the rectifying device occurs can be obtained.

Pressure-contact type rectifier with contact friction reducer

By using a small number of needles and contact terminals at burn-in, electric contact check is performed between each needle and each terminal provided in each semiconductor chip, and thereby the yield of assembled products can be improved. A packaging structure in which, for example, a volatile memory chip and a nonvolatile memory chip are formed is assembled in accordance with a production scheme in which burn-in of each memory chip is performed while still under the state of a semiconductor wafer, and by forming the packaged structure using the good volatile memory chip subjected to burn-in and likewise, also, the nonvolatile memory chip. At this burn-in, contact check is performed by bringing a needle, provided in a burn-in board, into contact with, for example, six test-only signal terminals of a test circuit formed on each semiconductor chip.

Semiconductor wafer, semiconductor chip, and manufacturing method of semiconductor device

A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.

Semiconductor device

A semiconductor memory device of a DDR configuration improved in glitch immunity and the convenience of use is to be provided. It is a dynamic type RAM the operation of whose internal circuit is controlled in synchronism with a clock signal; an input circuit is provided in which a second clock signal inputted when in write operation is used to take in a plurality of write data serially inputted in response to that signal into a plurality of first latch circuits, and said first clock signal is used to take the write data taken into the first latch circuits into the second latch circuit to convey them to an input/output data bus; a logic circuit is provided to mask, in accordance with the logic of the first clock signal and the second clock signal, any noise arising at the end of the second clock signal, and a third clock signal is generated and supplied to the first latch circuits which output the write data to at least the input of the second latch circuits.

An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

Semiconductor memory device of DDR configuration having improvement in glitch immunity

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on a small voltage difference of input signals being amplified in two stages and the amplifying circuit being 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

Sense amplifier circuit

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being a 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

A static RAM has plurality of memory mats each including a plurality of static memory cells formed in a matrix pattern at points of intersection between a plurality of word lines and a plurality of data lines. upon receipt of an address signal into an address register, an address selection circuit selects a memory cell in one of the memory mats, and connects the selected memory cell to a sense amplifier or a write amplifier furnished corresponding to the memory mat in question. At the same time, an address counter generates an address signal corresponding to the address signal by which one of the memory mats has been selected. When a burst mode is designated by a control signal, the address signal admitted to the address register is used to select a memory cell in a first memory mat. The selected memory cell is connected to the corresponding sense amplifier or write amplifier. Then in accordance with the address signal generated by the address counter, a memory cell in another memory mat is selected and connected to the corresponding sense amplifier or write amplifier.

Static random access memory

A sense amplifier, which is intended to reduce the output response time after it has received a small voltage difference until it delivers amplified output signals, consists of a latch circuit made up of a pair of CMOS inverters, a pair of NMOS transistors connected in parallel to the latch circuit, and a current source connected in series to the latch circuit and NMOS transistor pair. The NMOS transistors amplify a small voltage difference of input signals, and the inverters of the latch circuit further amplify the resulting voltage difference to produce the output signals. Based on is a small voltage difference of input signals being amplified in two stages and the amplifying circuit being of 2-stage serial connection of the current source and the NMOS transistor or CMOS inverter, the delay time of output response can be reduced.

Growing community of inventors

Fussa, Japan

Takahiro Sonoda