Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Fujitsu Corporation

Meidensha Corporation

Kioxia Corporation

Tokyo Ohka Kogyo Co., Ltd.

Lapis Semiconductor Co., Ltd.

Oki Semiconductor Co., Ltd.

Takahiro Shimizu

Noboru Shibata

Akira Nakagawa

Kimihiko Kazui

Eishi Morimatsu

Yasushi Washio

Weihan Wang

Shigeo Watanabe

Hiroshi Maejima

Toshihiro Suzuki

Hiroshi Sukegawa

Tokumasa Hara

Yoshiyuki Utsumi

Hiroshi Yao

Akio Sugahara

Naomi Takeda

Toshio Yamamura

Takayoshi Mori

Daiki Watanabe

Yasushi Kuroiwa

Shota Katayama

Yuko Utsunomiya

Kenji Kawakubo

Yoshihiko Shindo

Manabu Sato

Yosuke Arai

A semiconductor memory device includes a memory string and a control circuit. The memory string includes a first memory cell connected to a first word line and a second memory cell adjacent to the first memory cell and connected to a second word line. The control circuit is configured to perform a multi-bit-data writing with respect to each of the first and second memory cells. The multi-bit-data writing includes, in order, a first programming to program the first memory cell, the first programming with respect to the second memory cell, a reading of first data from the first memory cell, a second programming to program the second memory cell, and a verification of data programmed in the second memory cell. The control circuit is configured to set a verify voltage to be applied to the second word line during the verification based on the first data.

Multi-bit writing and verification in semiconductor memory device

According to one embodiment, an electronic component includes an element, a first lead, and a second lead. The element includes a first electrode and a second electrode. The first lead is electrically connected with the first electrode, and has a flattened cross section. The second lead is electrically connected with the second electrode. The first lead includes a first connection portion, a first bonding portion, and a first extension portion. The first connection portion is connected with the first electrode. The first bonding portion is configured to be bonded with a substrate. The first bonding portion extends in an extension direction perpendicular to a first counter direction. The first counter direction connects the first electrode and the second electrode. The first extension portion is located between the first connection portion and the first bonding portion. The first extension portion extends in the extension direction.

Electronic component and electronic device

A semiconductor device including: a voltage detection section that outputs a first voltage and a second voltage that is different from the first voltage, the first voltage and the second voltage being voltages of a connected battery; a correction section that, on the basis of potential differences between the first voltage and second voltage, derives second data from first data, the first data representing a relationship between remaining battery levels and open circuit voltages, and the second data representing a relationship between remaining battery levels and battery voltages; and a calculation section that calculates a remaining level of the battery on the basis of a remaining battery level corresponding to a minimum voltage in the second data and outputs the calculated remaining level of the battery.

Semiconductor device and remaining battery level detection method

A semiconductor storage device includes a first memory string having first, second, and third memory cells and a first select transistor, a second memory string having fourth, fifth, and sixth memory cells and a second select transistor, a third memory string having seventh, eighth, and ninth memory cells and a third select transistor, a first word line connected to gates of the first, fourth, and seventh memory cells, a second word line connected to gates of the second, fifth, and eighth memory cells, and a third word line connected to gates of the third, sixth, and ninth memory cells. A write operation for writing multi-bit data in the memory cells includes first and second write operations. In the second write operations performed through the first, second, and third word lines, respective ones of the first, fifth, and ninth memory cell are initially selected.

Semiconductor storage device and memory system

A permanent magnet rotating electric machine is provided with: a magnet portion comprising a plurality of permanent magnets forming a plurality of sets each of which is attached annularly and which are disposed along an axial direction of a rotor; and a plurality of anti-scattering rings press-fitted along the axial direction around the outer circumference of the magnet portion forming the plurality of sets. The anti-scattering rings each have: an insulation coating provided on both side surfaces contacting adjacent, other anti-scattering rings; a chamfer provided between the outer circumferential surface and one side surface; and an insulation coating provided on the chamfer.

Permanent magnet rotating electric machine

A dynamometer () in a dynamometer device () is assembled on the top of a dynamometer-side bed (), and the dynamometer-side bed () is removably attached to a tank-side bed () located on the top part of a bed tank (). Consequently, at the time of the disassembling of the dynamometer device () for maintenance or the like, it is possible to easily separate a dynamo body () and the bed tank () from one another by simply taking down the dynamometer-side bed () from the tank-side bed ().

Dynamometer device and method for assembling same

In a dynamometer device (), a dynamometer () is placed on a dynamometer-side bed (), and the dynamometer-side bed () is stacked on a tank-side bed () located on the top part of a bed tank (). The dynamometer () is connected to the bed tank () by an oil discharge pipe () which returns a cooling oil () to the bed tank () from the dynamometer (). The oil discharge pipe () passes through an interface () between the dynamometer-side bed () and the tank-side bed (), and extends into the bed tank ().

Dynamometer device

A semiconductor memory device includes memory cells, a sense amplifier unit including a first latch circuit, and a control unit configured to execute read and write operations on the memory cells. The control unit, while executing the write operation on the memory cells, responsive to a write suspend command followed by a read command, performs a data saving operation, the read operation, and a data restoring operation prior to resuming the write operation. The data saving operation includes transferring first data stored in the first latch circuit to an external device, the first data including at least a result of verify operation performed on the memory cells. The data restoring operation includes transferring the first data to the first latch circuit.

Semiconductor memory device and memory system

A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.

Semiconductor memory device

A memory system includes a memory device, and a controller which controls the memory device. The memory device includes a plurality of memory cells capable of rewriting data, a plurality of word lines connected to the plurality of memory cells, a page including the plurality of memory cells connected to the same word line, a plane including a plurality of pages, a memory cell array including a plurality of planes, and a plurality of word line drivers which apply voltages to the plurality of word lines, and a plurality of switches provided for each plane and which assigns the word line drivers to the word lines.

Memory system

A chemically amplified positive-type photosensitive resin composition capable of suppressing the phenomenon of footing in which the width of the bottom (the side proximal to the surface of a support) becomes narrower than that of the top (the side proximal to the surface of a resist layer) when a resist pattern serving as a template for a plated article is formed on a metal surface of a substrate using the composition. A mercapto compound is contained in the composition which includes an acid generator capable of producing an acid when irradiated with an active ray or radiation and a resin whose solubility in alkali increases under the action of acid.

Chemically amplified positive-type photosensitive resin composition

A semiconductor memory device includes a memory which comprises a confidential information area storing confidential information and a flag. A controller reads the flag from the memory when instructed to erase or write data in the confidential information area, determines whether the flag is set, erases or writes data in the confidential information area when the flag is clear, and abandons a process requested by an erase or write instruction when the flag is set. An authenticator uses data in the confidential information area to execute an operation for authentication. A management information area may store management information for associated pages. The flag may include a bit string and a complementary bit string to improve reliability of the flag. The confidential information area may store dummy data when the memory is used for uses other than an application with an authentication function, so no problem arises using a normal controller.

Semiconductor memory device including a flag for selectively controlling erasing and writing of confidential information area

According to one embodiment, a semiconductor memory system includes semiconductor memories, and a memory controller configured to control the semiconductor memories. Each of the semiconductor memories is configured to execute an internal sequence including operations and have a wait period after an end of each of the operations, to notify, during the wait period, a status signal, which notifies in advance a start of a next operation, to the memory controller, and to start the next operation upon receiving a restart instruction of the internal sequence from the memory controller.

Semiconductor memory system with current consumption control

What is provided is a positive-type photoresist composition containing an acid generator (A) capable of generating an acid when irradiated with an active ray or radiation, a resin (B) whose solubility in alkali increases under the action of acid, and an organic solvent (S), the photoresist composition further containing an alkali-metal salt (C).

Growing community of inventors

Yokohama Kanagawa, Japan

Takahiro Shimizu