Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Matsushita Electric Industrial Co., Ltd.

Takahiro Shima

Hirofumi Nishimura

Junji Sato

Toshifumi Nakatani

Kenji Miyanaga

Masakatsu Maeda

Naoya Yosoku

Hiroshi Komori

Masashi Kobayashi

Taiji Akizuki

Yoshito Hirai

Masaki Kanemaru

Takeaki Watanabe

Yoichi Nagaso

Tosiakira Andou

The present disclosure provides a moving object detection device including a first input circuitry that receives positional information indicating a position of an object present around a vehicle in time sequence from an object detector included in the vehicle, and a controller that processes the positional information received by the first input circuitry in time sequence, detects at least a first continuum along a traveling road of the vehicle, and when a shape of a detected first continuum of this time is changed in comparison with a shape of a previous first continuum, outputs information indicating that another moving object different from the vehicle is present to a vehicle control circuitry of the vehicle.

Moving object detection device, program, and recording medium

There is provided a detection device that includes: a position estimator that estimates a candidate position of a crosswalk in a movement direction of a vehicle and estimates a length of the crosswalk and an intersecting angle between the crosswalk and a roadway using the candidate position; a corrector that corrects the numbers of periods and widths of two basis functions based on the estimated length of the crosswalk and the estimated intersecting angle, the two basis functions corresponding to intervals of white lines of the crosswalk and are orthogonal to each other; and a crosswalk detector that detects whether or not the crosswalk is present using both image data which include the candidate position and the two corrected basis functions.

Detection device and detection method

A gain control circuit includes: a gain switching controller that changes the gains of a fundamental frequency amplifier and an N-multiplied frequency amplifier; and a detection voltage comparator that determines whether the operating state of an N-multiplier is a saturated operation or a linear operation. The detection voltage comparator determines the operating state of the N-multiplier by comparing an amount of change in a detection signal (first detection signal) representing a fundamental frequency signal with respect to an amount of change in the gain of the fundamental frequency amplifier with an amount of change in a detection signal (second detection signal) representing a high-frequency signal with respect to the amount of change in the gain of the fundamental frequency amplifier. The gain switching controller adjusts the gains of the fundamental frequency amplifier and the N-multiplied frequency amplifier on the basis of the operating state of the N-multiplier.

Output control circuit

In the stop state of a VCO and an injection locked frequency divider, an ILFD controller sets the control parameter of an injection locked frequency divider on the basis of the frequencies of a reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider. While the injection locked frequency divider is operated and in the stop state of the VCO, the ILFD controller sets the control parameter of the injection locked frequency divider on the basis of the frequencies of the reference signal and the frequency-divided signal measured according to the control parameter of the injection locked frequency divider.

PLL circuit, calibration method, and wireless communication apparatus

An injection locked frequency divider includes a ring oscillator, an input terminal, an output terminal and a control voltage terminal. The ring oscillator has a three-stage cascade connection of a first amplification circuit including an N-channel MOS type transistor and P-channel MOS type transistors, a second amplification circuit configured in the same manner as the first amplification circuit and a third amplification circuit configured likewise. A high frequency signal is input to a gate terminal of each P-channel MOS type transistor. A predetermined DC control voltage is supplied to a gate terminal of each P-channel MOS type transistor.

Injection locked oscillator

An ILFD control unit sets a control parameter of an injection locked frequency divider based on each frequency of a reference signal and a frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in a stop state of a VCO and an injection locked frequency divider. The ILFD control unit runs the injection locked frequency divider and sets a control parameter of the injection locked frequency divider based on each frequency of the reference signal and the frequency-divided signal measured in response to the control parameter of the injection locked frequency divider, in the stop state of the VCO.

Semiconductor

An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider.

PLL circuit, calibration method and wireless communication terminal

An injection locked frequency divider and a PLL circuit, having a wide operating frequency bandwidth and capable of reducing the influence of any parasitic capacitance, are provided. Injection locked frequency divider () includes ring oscillatorthat cascade-connects first amplifier circuit () including N-channel MOS transistor () and P-channel MOS transistor (), and second amplifier circuitand third amplifier circuit () that have the same configuration as first amplifier circuit () in three stages in a ring; N-channel MOS transistorin which the sources of N-channel MOS transistors () in the respective stages are connected to the drain thereof; and differential signal injection circuit () that injects injection signal Ito the gates of P-channel MOS transistors () in the respective stages and injects a reverse phase signal of injection signal Ias a differential signal to the gate of N-channel MOS transistor ().

Injection locked frequency divider and PLL circuit

A frequency conversion circuit is provided capable of suppressing noise converted from about a frequency twice as large as a local signal to a reception band frequency, which performs modulation by mixing an input signal with a local signal. The frequency conversion circuit includes a first transistor whose base is electrically connected with one of a first input terminal pair inputted with the input signal; a second transistor whose base is electrically connected with the other of the first input terminal pair; third and fourth transistors whose emitters are electrically connected respectively with a collector of the first transistor; fifth and sixth transistors whose emitters are electrically connected respectively with a collector of the second transistor; and a differential noise suppression circuit provided between the collector of the first transistor and the collector of the second transistor. The differential noise suppression circuit includes at least one capacitor, which suppresses a differential noise component of a frequency twice as large as a local signal frequency without repeating charging or discharging of the capacitor with at least the local signal frequency.

Frequency conversion circuit, modulation circuit, polar modulation transmitting circuit, quadrature modulation transmitting circuit, communication instrument, and frequency conversion method

Growing community of inventors

Kanagawa, Japan

Takahiro Shima