Fujitsu Corporation

Takahiro Shikibu

Osamu Moriyama

Gen Oshiyama

Iwao Yamazaki

Akihiro Chiyonobu

Tatsumi Nakada

Yusuke Hamada

The processor includes core circuits and a cache unit having L2 to LN caches (N is 3 or more). L1 cache has a move-in buffer including entries in which memory access instruction resulted in cache miss in L1 cache is stored. The move-in buffer, when issuing a normal memory request to L2 cache, issues a pseudo memory request to L3 to LN caches in parallel and receives a pseudo data response that has coherency-unsecured data from any one cache. The re-order buffer executes a normal instruction execution completion process in response to the normal data response, executes a pseudo instruction execution completion process in response to the pseudo data response, and, when the pseudo data response is a failure, rewinds an arithmetic operation circuit that speculatively executed instructions after the memory access instruction in response to the pseudo instruction execution completion process, back to a state before the speculative execution.

Processor

A semiconductor apparatus that selects a first packet from a plurality of packets stored in a buffer and transfers the first packet. The semiconductor apparatus switches a plurality of different conditions for grouping the plurality of packets according to a priority order of the plurality of conditions; and selects the first packet from a plurality of packets pertaining to a group extracted on a condition selected by the switching according to a given selecting scheme, and transfers the first packet from the buffer.

Semiconductor apparatus and transfer method

A semiconductor device, includes: a first semiconductor chip including: a first substrate; a first via; a first rear surface-side pad connected to the first via; a first wiring layer; a first front surface-side pad formed on the first wiring layer; and an input circuit formed in the first substrate, an input signal wire connecting the first via, the first front surface-side pad, and an input terminal of the input circuit; and a second semiconductor chip including: a second substrate; a second wiring layer; a second front surface-side pad; and an output circuit formed in the second substrate, an output signal wire connecting the second front surface-side pad to an output terminal of the output circuit. The second semiconductor chip is stacked on a rear surface side of the first semiconductor chip, and the first rear surface-side pad and the second front surface-side pad are connected.

Semiconductor device having a plurality of chips being stacked

A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

Test circuit and method for controlling test circuit

A semiconductor device includes: a plurality of semiconductor chips; and a connecting portion that connects a plurality of terminals formed on the plurality of semiconductor chips, wherein the plurality of terminals of the plurality of semiconductor chips belong to one of first group or second group, an interval between one of first terminals belonging to the first group and one of second terminals belonging to the second group is a predetermined interval, the one of the second terminals being adjacent to the one of the first terminal, the first terminals are arranged at an interval larger than the predetermined interval, and each of the plurality of semiconductor chips includes a selecting portion that selects a signal transmitting terminal among the plurality of terminals, per each of the groups.

Semiconductor device and method of testing semiconductor device

A test circuit, provided to a semiconductor device including a plurality of semiconductor chips, includes: a test clock terminal provided to a first chip; a plurality of clock paths disposed between the first chip and a second chip through which the test clock is transmitted from the first chip to the second chip; a test unit provided to the second chip for testing the second chip by using the test clock transmitted to the second chip; a clock detection unit provided to the second chip, and detects the test clock that is received through each of the plurality of clock paths; and a clock path selection unit which is provided to the second chip, selects a first clock path among the plurality of clock paths as a test clock path, and supplies the test clock transmitted through the test clock path to the test unit.

Test circuit and method of controlling test circuit

A semiconductor device includes chips, wherein a first chip: an internal circuit; first selectors to output signals from one of first outputs; second selectors to output signals from one of second outputs; first output buffer units to relay/interrupt signals output from one of the first outputs; second output buffer units to relay/interrupt signals output from one of the second outputs; first terminals to output a signal from the respective first output buffer units and belong to a first group in which the first terminals are placed at positions distant by first distances; and second terminals to output a signal from the respective second output buffer units and belong to a second group in which the second terminals are placed at positions distant by second distances and each of the second terminals is placed at a position distant from an adjacent first terminal of the first terminals by third distances.

Growing community of inventors

Kawasaki, Japan

Takahiro Shikibu