Fujitsu Corporation

Takahiro Ohyama

Akihito Kobayashi

Motohiro Sakai

Takuro Kumabe

Shinichiro Matsumura

When an access process has been requested for a storage apparatus, a registration unit determines an access priority of the requested access process and registers an entry corresponding to the requested access process in a queue corresponding to the determined access priority out of a plurality of queues that are each provided for a different access priority. An instruction unit checks the plurality of queues at intermittent check timing, fetches, at each check timing, one entry from each queue, out of the plurality of queues, in which entries are registered, and instructs the storage apparatus to execute access processes corresponding to the fetched entries.

Storage control apparatus and storage control method

A control device includes a processor. The processor is configured to collect plural types of performance information regarding a first data unit. The processor is configured to determine, on basis of the collected plural types of performance information, whether to transfer the first data unit from a first storage device which is under control of a first controller to a second storage device which is positioned as higher than the first storage device. The processor is configured to transfer the first data unit from the first storage device to the second storage device depending on a result of the determination.

Control device and storage system

A control unit stores data used in a process to a shared cache memory. The control unit provides a shared queue in a memory space of the shared cache memory and performs LRU control with the use of the shared queue. The control unit also provides a local queue in the memory space of the shared cache memory. The control unit enqueues a CBE (management information) for a cache page used by a core in a process to the local queue. The control unit dequeues a plurality of CBEs from the local queue upon satisfaction of a predetermined condition, and enqueues the dequeued CBEs to the shared queue.

Apparatus and method for controlling shared cache of multiple processor cores by using individual queues and shared queue

An apparatus includes a first cache memory, a second cache memory, and a processor coupled to the first cache memory and the second cache memory, and configured to store data in the second cache memory, the data being deleted from the first cache memory, store first data stored in a first address of the storage device, in the second cache memory, in case where the first address is included in first management information and is not included in second management information, according to a request for access to the first address of the storage device, the first management information including an address in the storage device of specific data stored in the storage device, and the second management information including an address in the storage device of data stored in both of the second cache memory and the storage device, and register the first address in the second management information.

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Kawasaki, Japan

Takahiro Ohyama