Mitsubishi Denki Kabushiki Kaisha

Takahiro Ohnakado

Satoshi Shimizu

Akihiko Furukawa

Takaaki Murakami

Yuji Ariyoshi

Satoshi Yamakawa

Manabu Tsukamoto

Tatsuo Oomori

Atsushi Fukumoto

Yasuhiro Kosasayama

A rotation state detecting device capable of detecting the direction of rotation of a rotating body includes first and second bridge circuits made up of magneto-resistance effect elements, a first comparator for detecting the increasing/decreasing direction of the center point voltage of the first bridge circuit, a second comparator for detecting the increasing/decreasing direction of the center point voltage of the second bridge circuit, a third comparator for detecting the difference between the center point voltage of the first bridge circuit and the center point voltage of the second bridge circuit, and logic value information deriving means for outputting '1' when the logic values of the outputs of the first comparator and the second comparator are both '1', outputting &#x201c;0&#x201d; when they are both &#x201c;0&#x201d;, and continuing to output the previous value at other times, the direction of rotation of the rotating body being determined on the basis of a combination of the outputs of the first, second and third comparators and the logic value information deriving means.

Rotation state detecting device and rotation state detecting method

A quarter wavelength transmission line is provided between a signal transmission line for transmitting a high frequency signal and a ground node. The quarter wavelength transmission line has a length equal to a quarter of an effective wavelength of an operation frequency of a semiconductor device. A surge absorbing element is connected between the quarter wavelength transmission line and an internal circuit. The signal transmission line is coupled to the internal circuit through a capacitor. A clamp circuit is provided between a power supply line and a ground line. The clamp circuit clamps the voltage difference between the power supply line and the ground line to a prescribed voltage level or less. A high frequency semiconductor device is thus implemented which is capable of preventing breakdown of an internal circuit element due to an electrostatic discharge phenomenon (ESD) without degrading high frequency characteristics.

Circuit protecting against electrostatic discharge

A sophisticated and highly reliable high-frequency Si-MOS semiconductor device having high electrostatic discharge (ESD) resistance. Lateral polysilicon diodes are connected between high-frequency I/O signal lines and the external supply voltage, VDD, and between the ground, GND, and the high-frequency I/O signal lines, respectively. The forward direction of the diodes is the direction from the high-frequency I/O signal line to the supply voltage, VDD, and the direction from the ground, GND, to the high-frequency I/O signal line, respectively.

Si-MOS high-frequency semiconductor device

A semiconductor integrated circuit device includes a silicon substrate having a first region and a second region identical in conductivity type to the first region and having a lower dopant concentration than the first region, a second MOS transistor on a main surface of the second region as a radio frequency switch circuit switching on and off input and output of a radio frequency signal, and a first MOS transistor on a main surface of the first region in a radio frequency circuit other than the radio frequency switch circuit. A high performance, highly reliable semiconductor integrated circuit with an RE switch circuit provided on a silicon substrate as a system on a chip.

Semiconductor integrated circuit

Memory cell gates are formed on the main surface of a semiconductor substrate via a gate isolation film. Source regions and drain regions are formed on both sides of the memory cell gates. The source regions have p impurity regions and n impurity regions while the drain regions have p impurity regions and n impurity regions. And the concentration of the p impurity regions is made higher than the concentration of the p regions while the concentration of the n impurity regions is made higher than the concentration of the n impurity regions.

Non-volatile semiconductor memory device and manufacturing method thereof

A semiconductor device having high ESD resistance includes an internal circuit, an I/O pad, a division circuit connected to a lead-in line connecting the internal circuit and the I/O pad for outputting an electric signal from first and second terminals corresponding to an electric signal applied to the lead-in line and a clamp circuit including an MOS transistor for cutting off conduction when a difference in voltage between electric signals sent between the terminals is smaller in absolute value than a threshold voltage of the MOS transistor, and conducts when the absolute value is at least equal to the threshold voltage.

Electrostatic discharge protection circuit for a semiconductor device

A nonvolatile semiconductor memory device is obtained of which tunnel oxide film can be made thinner and which can allow low voltage and power consumption. P type polycrystal silicon is used as a floating gate electrode. Thickness of a tunnel oxide film (first insulating film) is set to less than 10 nm. By using P type polysilicon as a material of the floating gate electrode, a barrier height of a well-type potential is increased from 3.1 eV to 4.4 eV, and thus the leak current is effectively prevented. Thus, the film thickness of the tunnel oxide film can be made less than 10 nm, and operating voltage can also be lowered. Therefore, reduction in power consumption and improvement in performance of the nonvolatile semiconductor memory device can be achieved.

Growing community of inventors

Hyogo, Japan

Takahiro Ohnakado