Matsushita Electric Industrial Co., Ltd.

Victor Company of Japan, Limited

Takahiro Ochi

Yasuhiro Ueki

Makoto Usui

Keisuke Tanaka

Hironori Deguchi

Yutaka Osada

Yoshinori Miyada

Takahiro Bokui

Takafumi Nakashiba

Mitsuhiko Ohta

Yutaka Murata

Mitsuko Takada

In a voltage drop analysis step S, the process calculates a temporal variation of a power source voltage supplied to each cell along a transmission path of a clock signal. In a delay variation rate ratio calculation step S, the process calculates a delay time variation of each cell according to the power source voltage variation. In a clock delay variation amount calculation step S, the process obtains the magnitude of jitter of the clock signal based on the delay time variation.

Clock jitter calculation device, clock jitter calculation method, and clock jitter calculation program

Crosstalk between tracks, land prepit leakage, and effects of recording power modulation can cause the wobble signal period to change irregularly, thereby producing jitter in the recording clock which is derived by frequency multiplying the wobble signal. This problem is resolved by a recording clock generating circuit having an arrangement to average the wobble signal period, a timer for generating a rectangular wave with substantially the same period as the average period, and a frequency multiplying PLL for multiplying the timer output. The period averaging arrangement in particular determines the approximate average period at every wobble period and reflects the phase difference between the wobble signal and the timer in the timer setting so as to improve recording clock stability.

Recording clock generating device and method thereof

A recording clock generation circuit includes a first phase comparator for detecting a phase difference between a wobble signal and a PLL internal signal; a first filter for smoothing an output from the first phase comparator; a VCO circuit for oscillating in accordance with the output smoothed by the first filter; a frequency divider for dividing a frequency of an output from the VCO circuit; a phase adjusting circuit for adjusting a phase of an output from the frequency divider; and a second phase comparator for detecting a phase difference between the wobble signal and a pre-pit signal, and outputting the phase difference to the phase adjusting circuit.

Recording clock generation circuit

Disposed in a single integrated circuit chip are a central processing unit (CPU) for performing instruction execution, an on-screen display (OSD) circuit for displaying character information on a display screen, a read only memory (ROM) which is arbitrarily divided into a first ROM storage space for use by the CPU and a second ROM storage space for use by the OSD circuit, a random access memory (RAM) which is arbitrarily divided into a first RAM storage space for use by the CPU and a second RAM storage space for use by the OSD circuit, and a common bus which is composed of a data bus and an address bus. The CPU, the OSD circuit, the ROM, and the RAM are connected to the common bus in such a way as to allow the CPU and the OSD circuit to acquire an exclusive right to use the ROM and the RAM. When the common bus is not in use by the CPU, a message that said common bus is made available to the OSD circuit is communicated from the CPU to the OSD circuit via a bus liberation signal line, and the OSD circuit obtains a right to use the common bus.

Microcomputer with a built in character display circuit and visual display unit using such a microcomputer

Growing community of inventors

Kyoto, Japan

Takahiro Ochi