Hitachi, Ltd.

Takahiro Nishiyama

Hiromichi Yamada

Tatsumi Yamauchi

Fumio Murabayashi

Yoshikazu Kiyoshige

Noriyasu Ido

Takashi Hotta

Hideo Sawamoto

Eiki Kamada

A floating-point arithmetic processing apparatus has a circuit for generating a limit value for normalization shift by subtracting an exponent of the minimum value of a normalized number from a value of an exponent of an intermediate result, and a circuit for generating, as a normalization shift number, smaller one of a shift number necessary for making the mantissa of the intermediate result a normalized number and the limit value for normalization shift. The floating-point arithmetic processing apparatus further has a circuit having a circuit for detecting a condition for overflow before the rounding process and a circuit for generating a value in the case of overflow, so that a predetermined value is delivered as a final result only when the overflow condition is detected before the rounding process but in the other case, a result obtained by performing the normalization process and the rounding process is delivered. When no overflow takes place before the rounding process but overflow occurs after the rounding process, the result obtained by performing the normalization process and the rounding process is delivered as a final result.

Floating-point arithmetic processing apparatus

A multiplying apparatus includes a Booth decoder for performing a second-order Booth decode on a multiplier, a Booth selector for generating a partial product except the two high-order digits from the output of the decoder and a multiplicand, a partial product corrector for correcting the two high-order digits of the partial product based on the multiplier and the multiplicand and outputting the corrected result, for cancelling a sign corrected portion of the negative partial product, and a carry save adder for being inputted with the outputs of the Booth selector and the outputs of the corrector and adding them.

Multiplying method and apparatus

To offer a floating-point addition/subtraction processing apparatus and a method thereof, capable of shortening the computation time, the floating-point calculation processing apparatus includes an approximate shift mount predicting unit for predicting a shift amount for normalization by using the input floating-point data to be addition/subtraction processed within an error of 1 bit, a shift error detecting unit for detecting a difference between the predicted shift amount and a correct shift amount, and an bit shifter for correcting a result, obtained by normalization using the predicted shift amount, by the detected difference of the two shift amounts, wherein a round-off determination and a shift amount calculation are processed in parallel before a normalization shift processing is executed.

Floating-point addition/substraction processing apparatus and method

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Ebina, Japan

Takahiro Nishiyama