Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Takahiro Nango

Hiroyuki Moro

Tohru Fukuda

Yoshihisa Kojima

Yukiyasu Tatsuzawa

Hideyuki Yamakawa

Takayuki Mori

Shingo Akita

Takami Sugita

According to one embodiment, a memory system includes a first storage area and a controller. The first storage area configured to store therein data sent from a host. The size of the first storage area is a first size larger than a second size. The second size is a size of a logical address space which is assigned to a memory system by the host. The controller is configured to change the second size in response to a request from the host while at least a part of data in the logical address space stays valid.

Memory system of increasing and decreasing first user capacity that is smaller than a second physical capacity

According to one embodiment, there is provided a memory system including a volatile memory and a controller. The volatile memory has 1to Kmemory banks (K is a natural number equal to or larger than 2) that are kept in a power-on state and (K+1)to Nmemory banks (N is a natural number larger than K) whose power state is changed. The power state is the power-on state or a power-down state. The controller performs wake-up operation for the (K+1)to Nmemory banks in parallel with access operation to the 1to Kmemory banks. The wake-up operation changes the power state from the power-down state to the power-on state.

Memory system and control method

According to one embodiment, a memory control device includes: queues in channels; first controller; generator; and second controller. The queues hold write commands for data pieces. The first controller causes: (i) when a read command is received, and until the write commands are held in the queues, the channels are synchronized with each other, and processes of the write commands become ready to be performed, a read process based on the read command prior to the write commands; and, (ii) when the processes of write commands become ready to be performed, synchronization of the channels and write processes for the data pieces based on the write commands. The generator generates error correction codes based on the data pieces when the channels are synchronized with each other and the processes based on the write commands are performed. The second controller writes the error correction codes on the storage medium.

Memory control device, storage device, and memory control method

According to one embodiment, a data storage apparatus includes a read module, an error detector and a controller. The read module is configured to read data from a flash memory, more precisely from a rewrite area and a write-back area, both provided in the flash memory. The error detector is configured to detect errors, if any, in the data read. The controller is configured to keep rewriting data, without correcting the errors the error detector has detected in the rewrite area of the flash memory.

Data storage apparatus and method for writing data

According to one embodiment, a data storage apparatus includes a flash memory and a controller for controlling the flash memory. The flash memory is configured to store data is written in units of a prescribed size. In order to write data smaller than the prescribe size, the controller first isolates attribute data from each save data item of the prescribed size, which has been read from any flash memory, and then stores the attribute data to an attribute data memory, and finally transfers the user data contained in the save data, to a save data memory.

Data storage apparatus and method of writing data

An integrated circuit includes an AD converter and a self-test circuit configured to test the AD converter. The self-test circuit includes a clock generator which generates a clock for allowing the AD converter to AD-convert an external sine wave signal externally input, a sine wave generator which generates an internal sine wave signal in digital form, a subtractor which determines a differential signal between the AD-converted external sine wave signal and the internal sine wave signal, a PLL device which allows a phase-locked loop receiving the differential signal as an input to control a phase of the internal sine wave signal such that the internal sine wave signal is in phase with the external sine wave signal, and a root mean square calculator which calculates a root mean square of the differential signal to generate a diagnostic signal corresponding to the AD converter.

Growing community of inventors

Hino, Japan

Takahiro Nango