Mitsubishi Electric Corporation

Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Materials Corporation

Takahiro Nakamoto

Takayuki Hisaka

Yoshiyuki Tanaka

Tetsuya Yagi

Hiroyuki Ikeda

Hitoshi Inaba

Koichiro Nishizawa

Toshihiko Shiga

Naoto Kitahara

Tasuku Sumino

Kouichirou Harada

Masanobu Asami

Yoshihisa Sawada

Yasuhiro Shatou

Kazutaka Hujiwara

Heisen Ryu

Nobuya Saruwatari

A field effect transistor according to the present invention includes a semiconductor layer including a groove, an insulating film formed on an upper surface of the semiconductor layer and having an opening above the groove and a gate electrode buried in the opening to be in contact with side surfaces and a bottom surface of the groove and having parts being in contact with an upper surface of the insulating film on both sides of the opening, wherein the gate electrode has a T-shaped sectional shape in which a width of an upper end is larger than a width of the upper surface of the insulating film.

Field effect transistor and method of manufacturing the same

A method of manufacturing a semiconductor device includes: forming lower-layer wirings for a transistor, a circuit element and a plurality of contact pads on a substrate independently of each other; forming a first feed layer over an entire surface of the substrate on which the lower-layer wirings are formed; patterning the first feed layer to form a test pattern connecting terminals of the transistor to the separate contact pads independently of the circuit element; making a test on the transistor in a stand-alone state by using the contact pad and the test pattern; and after the test, connecting the transistor and the circuit element to form a circuit.

Method of manufacturing semiconductor device

A semiconductor device includes: a semiconductor substrate; an underlying wiring on the semiconductor substrate; a resin film extending to the semiconductor substrate and the underlying wiring, and having a first opening on the underlying wiring; a first SiN film on the underlying wiring and the resin film, and having a second opening in the first opening; an upper layer wiring on the underlying wiring and part of the resin film; and a second SiN film on the upper layer wiring and the resin film, and joined to the first SiN film on the resin film. The upper layer wiring includes a Ti film, connected to the underlying wiring via the first and second openings, and an Au film on the Ti film. The first and second SiN films circumferentially protect the Ti film.

Semiconductor device

A field effect transistor includes a pair of ohmic electrodes and an n-type GaAs layer between the pair of ohmic electrodes and having recesses. Crank-shaped gate fingers are located within the recesses of the n-type GaAs layer between the pair of ohmic electrodes, and each crank-shaped gate finger includes perpendicular-extending portions and parallel-extending portions relative to the [0,,] crystal orientation of the n-type GaAs layer. The portion of the n-type GaAs layer between the gate fingers continuously extends from input ends of the gate electrodes to terminal ends of the gate electrode. A non-active region is located around each perpendicular-extending portion of the gate fingers.

Field effect transistor having a crank-shaped multigate structure

An MESFET is configured wherein a semiconductor layer structure including an i-AlGaAs buffer layer, an n-AlGaAs electron supply layer having an impurity doping density ranging from 1&#xd7;10cmto 1&#xd7;10cmand a layer thickness ranging from 1 nm to 10 nm, and an n-GaAs channel layer, all of which are sequentially deposited from the semi-insulating GaAs substrate side, is disposed on the semi-insulating GaAs substrate, a gate electrode is provided on the n-GaAs channel layer, and a source electrode and a drain electrode opposite to each other with the gate electrode interposed therebetween are provided.

Field effect transistor

The invention relates to a surge absorber provided with; a surge absorber element composed of a columnar non-conductive member and a conductive film formed dividedly via a discharge gap on a peripheral surface of the non-conductive member, a pair of sealing electrodes disposed at opposite ends of the surge absorber element and touching the conductive film, and a glass tube with opposite ends closed by the sealing electrodes, and the surge absorber element and an inert gas encapsulated thereinside. In the surge absorber of the invention, a face of each sealing electrode which contacts with the surge absorber element is formed in a concave shape symmetrical with a central axis of the glass tube. As a result the surge absorber element can be positioned in the center of the glass tube with high accuracy, the life span and the surge current capacity of the surge absorber can be improved, and low cost and small size becomes possible.

Surge absorber and production method thereof

A chip-type surge absorber and method for producing same, wherein the chip-type surge absorber includes an insulating substrate in the shape of a rectangular parallelepiped; an insulating hermetic cap open at a bottom side thereof, for forming, together with the insulating substrate, a box-shaped hermetically sealed cavity filled with a discharge gas; terminal electrodes disposed at both ends in the hermetically sealed cavity; a pair of discharge electrodes which are formed in the hermetically sealed cavity such that a discharge gap is formed between the discharge electrodes and such that the discharge electrodes are electrically connected to corresponding terminal electrodes; and connection surfaces for increasing the connection area for the connection between the discharge electrodes and the terminal electrodes.

Chip-type surge absorber and method for producing the same

A semiconductor device having a gate electrode having a leg with two mutually offset portions is formed by successively depositing on a semiconductor substrate an amorphous material and a crystalline metal layer. A portion of the crystalline metal layer is removed photolithographically and the amorphous material is etched to form a hole extending to the semiconductor substrate. The through hole is filled when a second amorphous material is deposited on the crystalline metal layer. A second hole is photolithographically prepared in the second amorphous material, partially aligned with the first hole and filled with a gate electrode material, and thereafter the second amorphous material, crystalline metal layer, and original amorphous material are removed, leaving a gate electrode having a leg with mutually offset portions.

Growing community of inventors

Tokyo, Japan

Takahiro Nakamoto