Hitachi, Ltd.

Renesas Technology Corp.

Hitachi Displays, Ltd.

Takahiro Nagano

Atsuo Watanabe

Hiroyuki Mizuno

Yoshinobu Nakagome

Masataka Minami

Tsutomu Yatsuo

Yoshiaki Yazawa

Saburo Oikawa

Atsushi Hiraishi

Takahide Ikeda

Kazushige Sato

Naohiro Momma

Hajime Akimoto

Shoji Shukuri

Hiroshi Fukui

Takeo Shiba

Takashi Akioka

Tatsuya Kamei

Shin Kimura

Akira Fukami

Akira Horie

Takuzo Ogawa

Takashi Nishida

Shuroku Sakurada

Masayoshi Naito

Toshio Miyazawa

Yutaka Kobayashi

Kazuo Yano

Ryuichi Saito

Yoshiro Mikami

Mitsuru Hiraki

Hiroshi Kageyama

Hideo Maejima

Kinya Mitsumoto

Keiichi Yoshizumi

Seigou Yukutake

Yutaka Misawa

Jin Onuki

Hisao Amano

Yoshiteru Shimizu

Hideo Satou

Fumio Sato

Yoshinori Aono

Ryuichi Izawa

Tomio Yasuda

Kouichi Seki

Mitsuo Yanagi

Isamu Sanpei

Sumio Kawakami

Hideo Honma

Michio Oue

Takehiro Ohta

Youkou Wakui

Kenichi Shoji

Masaru Nakagawa

Yukimasa Sato

An image display device incorporates a group of pixels of two or more types, each pixel including a light source whose primary wavelength is specific to the type of pixel; a generating device for generating analog pixel signals to be input to the group of pixels from input digital pixel data, wherein the generating device has a converter to convert input digital pixel data into different output digital pixel data appropriate for each type of pixel where the output digital pixel data contains more bits than the input digital pixel data; and an input device for inputting the analog pixel signals to the group of pixels, each pixel including a light emission driver for driving the light source according to the analog pixel signal. An organic EL display device having individual R, G, and B light emission elements enables displaying in desired colors and controllable tones with reduced packaging area for the components of the organic EL display.

Image display device

A semiconductor integrated circuit includes a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.

Semiconductor integrated circuit device and microcomputer

A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.

A semiconductor integrated circuit include a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.

A liquid-crystal display apparatus includes first and second substrates sandwiching a liquid-crystal, and having a switching element provided at a cross point of a scan line and a data line on the first substrate, a vertical drive circuit for controlling a voltage of the scan line provided on the first substrate, a horizontal drive circuit for controlling a voltage of said data line provided on the first substrate, and a transparent electrode provided on a surface of the second substrate. The horizontal drive circuit includes a reference-voltage generator, a voltage selector, a controller, and a sample-and-hold arrangement.

Liquid-crystal display apparatus incorporating drive circuit in single integrated assembly

A semiconductor integrated circuit includes a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on operation mode. The control circuit receives a reference clock signal and controls first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit corresponds to the frequency of the reference clock signal.

A semiconductor device and a computer system, incorporating the same, is capable of capturing an external signal at a high speed and stably operating independent of the duty ratio of a clock signal. An external signal ADD is captured into an address latch 22 by a level latch. The level latch is controlled to a through state at the timing in which the external signal is decided and controlled to a latched state in the decision period of the external signal. A pulse generation circuit controls the timing for switching a latch to the through state to a desired timing by a pulse generation circuit 30 in a chip. According to the above structure, the capture of the external signal ADD can be accelerated because the capture of the signal is determined by the setup timing. Moreover, because a latching period is controlled by the pulse generation circuit in the chip, operations are performed in a stable manner without having to depend upon the pulse width of an external clock CLK.

Semiconductor device capable of holding signals independent of the pulse

A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.

Semiconductor device having semiconductor elements formed in a

A semiconductor device includes a plurality of semiconductor regions of a first conductive type and a plurality of semiconductor regions of a second conductive type. AMOS transistor having a channel of the second conductive type is formed in the semiconductor regions of the first conductive type, and a bipolar transistor and a MOS transistor having a channel of the first conductive type are formed in the semiconductor regions of the second conductive type. Each of the semiconductor regions of the first conductive type is made up of a semiconductor layer where the impurity concentration decreases with the depth from the surface thereof, a first buried layer of the first conductive type which is formed in a semiconductor substrate and where the impurity concentration distribution in the direction of thickness has a single peak value, and a second buried layer of the first conductive type which is formed between the semiconductor layer and the first buried layer and where the impurity concentration distribution in the direction of thickness has a single peak value. The first and second buried layers are formed by the ion implantation method, after an epitaxial growth process and a field oxidation process have been completed.

Method of fabricating bipolar transistor having high speed and MOS

A novel gate circuit is disclosed. A first semiconductor switch includes a couple of main terminals connected between a first potential level and an output node, in which a high impedance state is held in response to an input signal having a first logic level and a second logic level, and the impedance state changes from high to low only during a transient period when the input signal changes substantially from the first to second logic level. A second semiconductor switch includes a couple of main terminals inserted between a second potential level different from the first potential level and the output node, in which a high impedance state is held in response to the input signal, and the impedance state changes from high to low only during a transient period when the input signal changes from the second to first logic level.

Gate circuit, semiconductor integrated circuit device and method of

To eliminate misfit dislocation occurring in a hetero-interface and to provide a bipolar transistor capable of a high speed operation, the bipolar transistor is configured such that the energy band gap is progressively narrowing from part of an emitter layer towards part of a collector layer through a base layer.

Bipolar transistor with a particular silicon germanium alloy structure

Growing community of inventors

Higashimurayama, Japan

Takahiro Nagano