Hitachi, Ltd.

Renesas Electronics Corporation

Nec Corporation

Hitachi Power Semiconductor Device, Ltd.

Mitsubishi Heavy Industries Limited

Renesas Technology Corp.

National Institute of Advanced Industrial Science and Technology

Astellas Pharma Gmbh

Takahiro Morikawa

Norikatsu Takaura

Kenzo Kurotsuchi

Masaharu Kinoshita

Motoyasu Terao

Yoshitaka Sasago

Akio Shima

Satoru Hanzawa

Nozomu Matsuzaki

Toshimichi Shintani

Yuichi Matsui

Takashi Kobayashi

Toshiyuki Mine

Yoshihisa Fujisaki

Kan Yasui

Hiroyuki Minemura

Naoki Watanabe

Riichiro Takemura

Ryo Sato

Naoki Yamamoto

Yumiko Anzai

Masakazu Sagawa

Toshiaki Morita

Mitsuharu Tai

Hiroyuki Yoshimoto

Kenichi Akita

Takeyuki Nagashima

Kenichi Kawaguchi

Eiji Kawaminami

Motoyuki Miyata

Sunao Imada

Hisao Hamaguchi

Yohei Seki

Ikumi Kuriwaki

Kazuyuki Kuramoto

Tomoyoshi Imaizumi

Mitsuaki Okumura

Takahiro Odaka

Hikaru Takami

Kohei Inamura

Hideyuki Watanabe

Hiroki Fukudome

Akira Imada

Hiroki Ishioka

Ryosuke Yamaoka

Takasumi Oyanagi

Hiroyuki Kakamu

Masahito Kitamura

Terumasa Inoue

Tomohiro Yoshinari

Tatsunori Murata

Koyo Kinoshita

Hidenobu Tsukagishi

Provided is a semiconductor device where an electric field applied to an electric field protection layer at a bottom of a trench gate electrode of an active region is relaxed and an avalanche withstand voltage is improved. The semiconductor device includes: an active region that has multiple gate trenches, a trench gate electrode in each gate trench, and a P body layer provided to a section other than the gate trenches; and a termination region disposed on the outer periphery of the active region. Additionally, an electric field protection layer is provided to the bottom of each gate trench of the active region, an electric field relaxation layer is between the active region and the termination region, the bottom surface of the electric field relaxation layer is shallower than that of the electric field protection layer, and the electric field relaxation layer is electrically connected to the P body layer.

Semiconductor device

[Problem] To provide a compound useful as an active ingredient of a pharmaceutical composition for treating pancreatic cancer. [Means for resolution] The present inventors have studied about a compound that is useful as an active ingredient of a pharmaceutical composition for treating pancreatic cancer and have found that a quinazoline compound has an excellent degradation-inducing action on a G12D mutant KRAS protein and a G12D mutant KRAS inhibition activity and can be used as a therapeutic agent for pancreatic cancer, thus completing the present invention. The quinazoline compound or a salt thereof of the present invention can be used as a therapeutic agent for pancreatic cancer.

Quinazoline compound for inducing degradation of G12D mutant KRAS protein

A semiconductor chip includes a semiconductor substrate made of SiC, a front surface electrode formed in a principal surface of the semiconductor substrate, and a rear surface electrode (drain electrode) formed in a rear surface of the semiconductor substrate. The front surface electrode is bonded to a wire, and includes an Al alloy film containing a high melting-point metal. The Al alloy film contains a columnar Al crystal which extends along a thickness direction of the Al alloy film, and an intermetallic compound is precipitated therein.

Semiconductor chip and power module, and manufacturing method of the same

A semiconductor device has an active region in which a plurality of unit cells are regularly arranged, each of the unit cells including: a channel region having a first conductivity type and formed over a front surface of a semiconductor substrate; a source region having a second conductivity type different from the first conductivity type and formed over the front surface of the semiconductor substrate in such a manner as to be in contact with the channel region; and a JFET region having the second conductivity type and is formed over the front surface of the semiconductor substrate on the opposite side of the channel region from the source region in such a manner as to be in contact with the channel region. The channel region is comprised of a first channel region and a second channel region higher than the first channel region in impurity concentration, over the front surface of the semiconductor substrate.

Semiconductor device and method of manufacturing the same

An aircraft communication system for performing communication between each of a plurality of devices installed in an aircraft, wherein the communication system is provided with a plurality of communication processing units provided corresponding to the plurality of devices and a plurality of communication lines for connecting between the communication processing units, the plurality of communication processing units being capable of bidirectional communication via the plurality of communication lines. Upon receiving a plurality of communication data from the plurality of communication lines, one of the communication processing units determines, on the basis of identification information included in the received plurality of communication data, whether the received plurality of communication data needs to be acquired and acquires the communication data determined to need to be acquired.

Aircraft communication system, aircraft communication method, and communication device

A vertical chain memory includes two-layer select transistors having first select transistors which are vertical transistors arranged in a matrix, and second select transistors which are vertical transistors formed on the respective first select transistors, and a plurality of memory cells connected in series on the two-layer select transistors. With this configuration, the adjacent select transistors are prevented from being selected by respective shared gates, the plurality of two-layer select transistors can be selected, independently, and a storage capacity of a non-volatile storage device is prevented from being reduced.

Non-volatile memory device and production method thereof

An object of the present invention is to provide a technique for suppressing thermal disturbance of a phase change memory device having a three-dimensional structure. In the phase change memory device having a three-dimensional structure, a material having a high thermal conductivity is used as a gate insulation film of a MOS transistor for selection, and causes heat transmitted to a Si channel layer from a phase change recording film to successfully diffuse to a gate electrode. In this way, since heat generated from a recording bit diffuses to a non-selected bit adjacent to it, it is possible to suppress thermal disturbance. BN, AlO, AlN, TiO, SiN, ZnO and the like are useful as a gate insulation film having a high thermal conductivity.

Phase change memory device

A superlattice phase change memory capable of increasing a resistance in a low resistance state is provided. The phase change memory includes a first electrode, a second electrode provided on the first electrode, and a phase change memory layer having a superlattice structure between the first electrode and the second electrode, the superlattice structure including to repeatedly formed layers of SbTeand GeTe. The phase change memory layer having the superlattice structure includes a SbTelayer containing Zr in contact with the first electrode.

Superlattice phase change memory including Sb2Te3 layers containing Zr

A technique capable of improving performances of a semiconductor memory device provided with a recording film having a super lattice structure is provided. The semiconductor memory device records information by changing an electric resistance of a recording film by use of a change in an atomic arrangement of the recording film. Moreover, the recording film is provided with a stacked layer portion in which a first crystal layer and a second crystal layer made of chalcogen compounds having respectively different compositions are stacked, an orientation layer that enhances an orientation of the stacked layer portion, and an adhesive layer that improves the flatness of the orientation layer.

Semiconductor memory device and manufacturing method of the same

For decreasing a recording current and suppressing a cross erase simultaneously, a three-dimensional phase-change memory for attaining higher sensitivity and higher reliability by the provision of a chalcogenide type interface layer is provided, in which an electric resistivity, a thermal conductivity, and a melting point of the material of the interface layer are selected appropriately, thereby improving the current concentration to the phase-change material and thermal and material insulation property with Si channel upon writing.

Semiconductor memory device

On an insulating film () in which a plug () as a lower electrode is embedded, a laminated layer pattern of an insulating film () made of tantalum oxide, a recording layer () made of Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced and an upper electrode film () made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film () between the recording layer () and the plug (), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer () can be achieved. Further, by using the Ge&#x2014;Sb&#x2014;Te based chalcogenide to which indium is introduced as the recording layer (), the difference in work function between the insulating film () and the recording layer () is increased, and the programming voltage of the phase change memory can be reduced.

On the same semiconductor substrate, a memory cell array in which a plurality of memory elements R having a chalcogenide-material storage layerstoring a high-resistance state with a high electric resistance value and a low-resistance state with a low electric resistance value by a change of an atom arrangement are disposed in a matrix is formed in a memory cell region mmry, and a semiconductor integrated circuit is formed in a logic circuit region lgc. This chalcogenide-material storage layeris made of a chalcogenide material containing at least either one of Ga or In of 10.5 atom % or larger to 40 atom % or smaller, Ge of 5 atom % or larger to 35 atom % or smaller, Sb of 5 atom % or larger to 25 atom % or smaller, and Te of 40 atom % or larger to 65 atom % or smaller.

There is provided a semiconductor storage device which is capable of further reducing a size of a memory cell, and increasing a storage capacity. Plural memory cells each including a transistor formed on a semiconductor substrate, and a variable resistive device having a resistance value changed by voltage supply and connected between source and drain terminals of the transistor are arranged longitudinally and in an array to configure a three-dimensional memory cell array. A memory cell structure has a double channel structure in which an inside of a switching transistor is filled with a variable resistance element, particularly, a phase change material. The switching transistor is turned off by application of a voltage to increase a channel resistance so that a current flows in the internal phase change material to operate the memory.

Semiconductor storage device

A recording layermade of a chalcogenide material which stores a high-resistance state of a high electrical resistance value and a low-resistance state of a low electrical resistance value is used as a memory element RM in a memory cell region, and it is formed so that a concentration of Ga or In of a first layerpositioned on a lower electrode TP side of the recording layeris higher than the corresponding concentration of a second layerpositioned on an upper electrodeside. For example, the recording layer is formed so that a content of Ga or In of the second layer is 5 atomic % or more smaller than that of the first layer. Also, a circuit which can reverse the voltage polarity between the upper electrode and the lower electrode in a set operation and a reset operation is provided.

Growing community of inventors

Hachioji, Japan

Takahiro Morikawa