Toshiba Memory Corporation

Kioxia Corporation

Takahiro Miomo

Hajime Yamazaki

Yasunori Nakamura

Prashob Ramachandran Nair

Makoto Domon

Mitsunori Tadokoro

Hiroyuki Yamaguchi

Shinji Yonezawa

Hirokazu Takeuchi

Akihiro Nagatani

A memory system includes a first nonvolatile memory, a first processor, and a second processor. The first processor sets a first assignment amount. The second processor performs access to the first nonvolatile memory, calculates a consumed amount which is an amount according to an operation time of the first nonvolatile memory in the access, and transmits a notification to the first processor when the consumed amount reaches the first assignment amount.

Memory system

A memory system includes a memory and a memory controller. The memory includes first and second parallel operation elements, each including a plurality of first and second storage regions, respectively, and first and second buffers, respectively. The memory controller performs operations on the memory based on first and second group information. The first group information defines first groups, each first group including one first storage region and one second storage region, and each second group including at least two first groups. The memory controller, in response to a host command targeting a first storage region, (i) acquires first data from the first buffer, and thereafter (ii) causes the memory to read out second data to the first buffer. The first storage region storing the first data and the second storage region storing the second data belong to different first groups and to the same second group.

Memory system configured with a synthesized logical block into which a plurality of data units forming an error correction frame are written

Memory system for controlling memory access based on access time of memory

According to one embodiment, a memory system includes a first memory including a message queue having first to naddresses (n&#x2265;2, n is natural number), a first pointer showing one of the first to naddresses, and a second pointer showing one of the first to naddresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an iaddress (n&#x2265;i&#x2265;2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1)address (j&#x2265;1, j is natural number) when first to jmessages are queued in the first to jaddresses.

Memory system using message monitoring and first and second namespaces

According to one embodiment, a memory controller includes a first controller issuing one command which includes read commands for reading data from a nonvolatile memory, a second controller sequentially issuing the read commands and a dummy command which continues the read commands when the one command is received, and a third controller sequentially executing the read commands and the dummy command and informing an information of a read error to the second controller when the read error occurred, the second controller informing a completion of the one command to the first controller when the command which corresponds to the read error is the dummy command.

Memory controller and memory device

Growing community of inventors

Kanagawa, Japan

Takahiro Miomo