Kabushiki Kaisha Toshiba

Kioxia Corporation

Toshiba Memory Corporation

Takahiro Kurita

Atsuhiro Kinoshita

Shinichi Kanno

Yuki Sasaki

Takao Marukame

Yoshifumi Nishi

Kosuke Tatsumura

Masamichi Suzuki

Hirotaka Nishino

Yusuke Higashi

Yuichiro Mitani

Tetsuya Sunata

Jiezhi Chen

Kazunari Kawamura

Daisuke Hashimoto

Shinobu Fujita

Shinichi Yasuda

Tetsufumi Tanamoto

Masataka Goto

Kazuya Matsuzawa

Daisuke Hagishima

Yuuichiro Mitani

Izumi Hirano

Takumi Fujimori

Hisaki Niikura

Kazunari Sumiyoshi

Junichi Hoshino

Kohei Okuda

According to one embodiment, a memory system includes a non-volatile memory and a data map configured to manage validity of data written in the non-volatile memory. The data map includes a plurality of first fragment tables corresponding to a first hierarchy and a second fragment table corresponding to a second hierarchy higher than the first hierarchy. Each of the first fragment tables is used to manage the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second fragment table is used for each of the first fragment tables to manage reference destination information for referencing the first fragment table.

Memory system and information processing system

A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.

Memory system and method

According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.

Memory system and write control method

A memory system may be connected to a host device. The memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory to reduce an amount of power consumption of the memory system based on a first instruction received from a host device connected to the memory system.

Memory system, information processing system, and host device

A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.

An information processing apparatus includes a network interface, a storage device, and a processor. The processor is configured to assign a plurality of zones in the storage device. Each of the zones is a contiguous physical address range of the storage device that is mapped to a contiguous logical address range. The processor is configured to generate zone management information for each of the plurality of zones, store content received from the origin server via the network interface, in one of writable zones and update a writable address of the zone management information for the one of the writable zones. The processor is configured to operate to transmit the received content, and control the storage device to delete data stored therein in units of a zone upon a predetermined cache clearing criteria being met.

Information processing apparatus and method

A memory system includes a nonvolatile memory, a volatile memory, and a memory controller. The volatile memory includes a write buffer. The memory controller receives commands stored in a queue by a host device from the queue. The memory controller receives a command stored in a queue by the host device from the queue and, in a state where first data not satisfying a write unit is stored in the write buffer, when receiving a first command for writing the first data to the nonvolatile memory from the queue, simultaneously writes the first data and second data acquired from the host device or a predetermined region of the volatile memory different from the write buffer to the nonvolatile memory.

Memory system with memory controller

According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to select a first mode as a write mode to write data from the host to the nonvolatile memory when the controller receives a first instruction from the host. In the first mode, n-bit data is written into a memory cell in a first area of the nonvolatile memory, n being a positive integer more than or equal to 1. The controller is configured to select another mode different from the first mode as the write mode when the controller receives a second instruction from the host.

Storage device having a controller configured to select modes as write modes based on received instructions, storage system, and control method

According to an embodiment, a storage device includes a plurality of memory nodes and a control unit. Each of the memory nodes includes a storage unit including a plurality of storage areas having a predetermined size. The memory nodes are connected to each other in two or more different directions. The memory nodes constitute two or more groups each including two or more memory nodes. The control unit is configured to sequentially allocate data writing destinations in the storage units to the storage areas respectively included in the different groups.

Storage device and storage method

A storage system includes a plurality of nodes, each of the nodes including one or more node modules each of which includes a nonvolatile storage, and a connection unit directly connectable to at least one of the nodes. The connection unit is configured to transmit an access request or an inquiry directed to a target node module, determine a length of an interval before re-transmitting the access request or the inquiry, based on a response indicating an operation status of the target node module, which is returned by the target node module in response to the access request or the inquiry, and re-transmits the access request or the inquiry after the interval of the determined length has passed.

Storage system including a plurality of nodes

According to one embodiment, a storage system comprises storages includes a first storage and a second storage, controllers connected to the storages and includes a first controller connected to the first storage, and packet transfer units connected to the controllers and includes a first packet transfer unit. When first data is read from the second storage, the first controller reserves a region for receiving first packets includes the first data in a memory, places a command for receiving the first packets in a first queue of the first packet transfer unit, stores a second packet for requesting sending of the first data in the memory, and places a command for sending the second packet in the first queue.

Storage system

According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.

Growing community of inventors

Sagamihara, Japan

Takahiro Kurita