Nec Corporation

Takahiro Kumura

Katsumi Kikuchi

Yuichi Nakamura

Jun Sakai

Hirofumi Inoue

Shigeki Shinoda

Manabu Kusumoto

Shin Tominaga

Masatake Takahashi

Dai Kobayashi

Junichiro Mataga

Soichiro Takata

Kanta Miyake

A piping diagnostic device according to an exemplary aspect of the present invention includes: criteria distribution generating means for generating a criteria distribution that is statistical data of criteria data of piping based on construction information about the piping, design information about the piping, and material information about the piping; changed-state distribution generating means for generating a changed-state distribution that is statistical data of changed-state data of the piping that have changed due to aging based on at least either vibration or dynamic pressure of the piping that have changed due to aging; measurement means for measuring at least either vibration or dynamic pressure of the piping; and determining means for determining deterioration of the piping based on the criteria distribution, the changed-state distribution, and at least either vibration or dynamic pressure of the piping.

Piping diagnostic device, piping diagnostic method, discriminant-problem optimizing device, discriminant-problem optimizing method, criteria distribution generating device, criteria distribution generating method, and storage medium

A leakage inspection device according to an aspect of the present disclosure includes: at least one memory storing a set of instructions; and at least one processor configured to execute the set of instructions to: determine a measurement time; measure vibration waveforms for the measurement time by using at least two sensors set to a pipe; calculate a cross-correlation function of the measured vibration waveforms; detect peaks of the cross-correlation function at least twice in the measurement time; and determine that leakage occurs in a case where the peaks are repeatedly detected in the measurement time.

Leakage inspection device, leakage inspection method, and storage medium

To acquire information relating to degradation of a pipe on the basis of information that can be acquired using a simple method. The analysis device according to one embodiment is provided with: a determining unit for determining whether or not the accuracy of a pipe network model based on information that includes a parameter that changes in value in accordance with degradation of a pipe satisfies a predetermined criterion; and a derivation unit for deriving information relating to degradation of the pipe, based on the parameter, if the accuracy satisfies the predetermined criterion.

Analysis device, analysis method, and recording medium storing a program for deriving information relating to degradation of a pipe

An apparatus, method and the like which enables to represent a pipe network transporting a fluid by use of electrical circuit network is provided. The pipe network analysis apparatus includes; processing circuitry configured to receive a pipe network model that represents a pipe network being constituted by one or more piping elements, convert at least one piping element to an element of an electric circuit being configured to represent a non-linear relation between a pressure and a flow rate of the fluid in the piping elements by use of a relation between a voltage and a current, and generate a model representing an electric circuit network expressing the pipe network, by use of the element of the electric circuit; and an output device configured to provide the model analyzable by a specific electric circuit simulator.

Pipe network analysis apparatus, pipe network analysis method, and storage medium

In order to keep the deterioration of water distribution pipes from progressing, a tap water management system is provided with: a water pressure detection unit for detecting the water pressure in at least one location in a water distribution pipe for carrying clean water from a water distribution site to a consumer. and transmitting the detection result as water pressure information; a deterioration detection unit for detecting deterioration in at least one location in a water distribution pipe, and transmitting the detection result as deterioration information; a water distribution planning unit for causing a water distribution plan that is a plan for water distribution pressure to be determined on the basis of information regarding past water demand; a deterioration-reducing water distribution planning unit for deciding, on the basis of the water distribution plan, the water pressure information, and the deterioration information. a deterioration-reducing water distribution plan according to the extent of deterioration; a water distribution pressure changing unit for changing the water distribution pressure of the water distribution pipe; and a water distribution pressure control unit for controlling the water distribution pressure changing unit on the basis of the deterioration-reducing water distribution plan.

Tap water management system, tap water management device, tap water management method, and tap water management program recording medium

There is provided a cache synchronization control method by which contents of a plurality of caches can be synchronized without a programmer explicitly setting a synchronization point, and the contents of the caches can be synchronized without scanning all cache blocks. A cache synchronization control method for a multiprocessor that has a plurality of processors having a cache, and a storage device shared by the plurality of processors, the method comprises: before a task is executed, a first step of writing back input data of the task to the storage device by a processor that manages the task and deleting data corresponding to the input data from its own cache by a processor other than the processor; and after the task is executed, a second step of writing back output data of the task to the storage device by a processor that has executed the task and deleting data corresponding to the output data from its own cache by a processor other than the processor.

Multiprocessor, cache synchronization control method and program therefor

It is possible to increase the processor instruction set design job efficiency and reduce workload on designers in investigation of an instruction set. An instruction operation code generation system includes an operation code bit width decision means, an instruction sorting means, and an operation code value decision means. The operation code bit width decision means decides a bit width that can be assigned for an operation code of each instruction according to specification data associated with a processor instruction set. The instruction sorting means sorts the instructions according to the operation code bit width. The operation code value decision means decides the value of the operation code of each instruction.

Instruction operation code generation system

To provide a decoding device that compactly stores prefix related information therein compatible to variable-length codes used in various systems. The decoding device includes a register file in which a prefix common portion and a word length of the prefix common portion, prefix individual portions and word lengths of the prefix individual portions, word lengths of suffixes, and an input bit sequence are stored, a bit matching unit that determines a prefix included in the input bit sequence from prefixes generated from the prefix common portion and the prefix individual portions, a codeword computation unit that computes the word length of a codeword included in the input bit sequence using the respective word lengths of the prefix common portion, a prefix individual portion, and a suffix corresponding to the determined prefix, and an index computation unit that computes an index in a symbol table using the respective word lengths of the corresponding suffix and the codeword.

Variable-length code determining device and variable-length code decoding method

Disclosed is an apparatus in which there are provided a first storage unit for storing signals to which indexes are given in order to distinguish each of a plurality of signals that are to be coded; a first index computing unit for computing first indexes of non-zero signals among the signals stored in the first storage unit; a second index computing unit for computing second indexes from a base index and the first indexes; a second index storage position search unit for searching for a storage position in a second storage unit in which the second indexes are to be stored based on values of the indexes stored in the second storage unit; a second index preserving unit for preserving the second index in the second storage unit based on a storage position searched for by the second index storage position search unit; and a control unit for giving the base index to the second index computing unit and for controlling operation of the first index computing unit, the second index computing unit the second index storage position search unit, and the second index preserving unit.

Encoding apparatus, method, and processor

Disclosed is a technology of converting a first assembly language program implementable on a first processor to a second assembly language program implementable on another processor. The two assembly language programs are described using same instructions. A unique address in the first assembly language program is assigned to a first number of bytes, and a unique address in the second assembly language program is assigned to a second number of byte numbers. The first number is larger than the second number. The first assembly language program is read from a storage. Thereafter, one or more address descriptions of the first assembly language program are translated to another one or more address descriptions using a ratio of the first number to the second number so that the first assembly language program is implementable on the second processor, wherein the ratio is 2 or a positive integer more than 2.

Method and computer program for converting an assembly language program for one processor to another

A complex symbol sequence (), which is a product of an orthogonally detected complex demodulated symbol sequence () and a conjugate complex number of a known symbol sequence (), is applied to phase rotating units () which change the phase of the complex symbol sequence () based on frequency offsets (fa, fb, fc). N-symbol adders () each add N symbol values supplied from the phase rotating units (), while M-power adders () each calculate the power of a value supplied from the N-symbol adders (), and add the power M times. A frequency offset control unit () controls frequency offsets applied to the phase rotating units () based on three power sums supplied from the M-power adders (), and delivers a power offset estimate ().

Frequency offset estimator

A synchronization establishing apparatus in a spectrum spread communication system, includes a search section that calculates correlation values from a received spectrum spread signal, and calculates power values and power addition values of the power values. Also, the search section selects larger ones of the power addition values to output together with timing data corresponding to the selected larger power addition values. One of the symbols and the power values is corrected in phase based on phase change quantities. A frequency offset estimating section estimates frequency offsets from one of the correlation values and the power values and demodulation timing data and calculates the phase change quantities from the estimated frequency offsets. A demodulation path selecting section selects path timings based on the selected larger power addition values and outputs the demodulation timing data to the frequency offset estimating section.

Spectrum spread communication synchronization establishing apparatus using frequency offset and receiver with the same

An object of the present invention is to provide a multiply-accumulate unit with a rounding function which is capable of effecting 16-bit multiply-accumulate operations taking into account the position of an addend in a register. The multiply-accumulate unit with the rounding function has a selection inputting and expanding means for expanding an addend from 31st-16th bits of 40-bit register into 40-bit data and transmitting the 40-bit data to MAC (multiply-accumulate) unit if control signal Position from an external source is &ldquo;1&rdquo;, and expanding an addend from 15th-0th bits of 40-bit register into 40-bit data and transmitting the 40-bit data to MAC unit if control signal Position is &ldquo;0&rdquo;. MAC unit performs a multiply-accumulate operation on the 40-bit data, 16-bit data multiplicand B, and multiplier C. Rounding and selection outputting means rounds off the result of the multiply-accumulation operation into 16-bit data if control signal Round from an external source is &ldquo;1&rdquo;, and outputs the rounded data to the position of the addend in the 40-bit register , where the position is indicated by control signal Position.

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Tokyo, Japan

Takahiro Kumura