Denso Corporation

Takahiro Iwamura

Masahiro Yamamoto

Osamu Katayama

Tsuneo Maebara

Yoshiyuki Hamanaka

Akimasa Niwa

Seiji Nishimoto

Takeshi Inoue

Tetsuo Hirano

Kohei Shinomiya

A transistor drive circuit drives a bipolar-type transistor and a MOSFET that are connected in parallel to each other. A temperature detection element that detects a temperature of a the bipolar-type transistor or the MOSFET. When the temperature is equal to or less than a threshold, the transistor drive circuit turns on both of the MOSFET and the bipolar-type transistor. When the temperature exceeds the threshold, the transistor drive circuit turns on only the bipolar-type transistor.

Transistor drive circuit and motor drive control apparatus

A drive control device for two semiconductor elements having a transistor structure and a diode structure with a common energization electrode includes: a current detection device outputting a current detection signal of the semiconductor elements; and a first control device outputting a gate drive signal from when a first time period has elapsed from a starting time to when a second time period has elapsed from the starting time, at which an off-command signal is input after it is determined that a current flows through the semiconductor elements in a forward direction of the diode structure during a time period for which an on-command signal is input to the semiconductor elements. The first and the second time periods are preliminary set not to generate an arm short-circuit between two semiconductor elements.

Drive control device

A transmission circuit transmits a header pulse signal which has signal length being equal to or more than twice as long as reference time, pulse period having predetermined ratio thereof to the signal length, and pulse stop period being successive and longer than the reference time via transmission path. The transmission circuit subsequently and successively transmits a plurality of data pulse signals which have signal length being the same as the reference time, pulse period having predetermined ratio thereof to the signal length associated with data, and pulse stop period being located before and after the pulse period via the transmission path. A reception circuit receives pulse signals via the transmission path, detects the header pulse signal based on the pulse stop period of the received pulse signal, and obtains a plurality of pieces of data based on the pulse period of pulse signals following the header pulse signal.

Information transmission apparatus

A hybrid power device is formed of a normally-on type SiC-JFET and a normally-off type Si-MOSFET, which are connected in cascode with a source of the SiC-JFET and a drain of the Si-MOSFET being connected to each other thereby forming a hybrid power FET. A gate of the SiC-JFET and a source of the Si-MOSFET are connected via a switching speed regulating resistor. A capacitor is connected to the switching speed regulating resistor in parallel to control a switching speed to a first speed in a former part of the switching period of the hybrid power FET and to a second switching speed in a latter part of the switching period. The second switching speed is lower than the first switching speed.

Hybrid power device

In a power conversion device having high side and low side switches connected to a coil, a direction of a coil current is determined during a dead time period where the respective switches turn off at the same time to make the increase/decrease ratio of the coil current correspond to a command value. Based on a direction detection signal and a PWM signal of a PWM signal generation unit, an operation mode of a power converter circuit is determined, and a ratio correction value and an offset value of the PWM signal is set with respect to a control period of the PWM signal. As a result, a change in the operation mode of the power converter circuit is detected to allow the increase/decrease ratio of the coil current to correspond to a command switching ratio.

Power conversion device

A communication system has a plurality of nodes that perform encrypted communication via a LAN, each using an identical common cipher key. The common cipher key is replaced at fixed or irregular intervals, by being transmitted from a main node in a broadcast mode via the LAN to respective secondary nodes that are to share the key. When the key is successfully received by a secondary node, it returns a confirmation signal. The system can be configured such that a notification list of secondary nodes for which key acquisition has been confirmed is transmitted to all of the secondary nodes.

Communication system having plurality of nodes sharing a common cipher key, cipher key dispatching apparatus for use in the system, and anti-theft apparatus utilizing information derived from cipher key utilization

A display panel having plural capacitive elements such as electroluminescent elements is driven by an integrated circuit connected between the display panel and a power source. A pair of power transistors such as MOSFETs is connected between the power source and the integrated circuit. The capacitive elements are selectively charged and discharged by operating switching elements in the integrated circuit. The pair of transistors disposed separately from the integrated circuit is turned on or off after the switching elements in the integrated circuit are closed, so that the switching loss only occurs in the transistors outside the integrated circuit, thereby suppressing temperature rise in the integrated circuit. A pair of resistors may be used in place of the transistors to divide a voltage supplied to the capacitive elements between the resistors and the integrated driver circuit. A step-recycle circuit including a condenser for recycling a part of energy stored in the capacitive elements may be further connected between the power source and the pair of transistors, to further reduce power consumption in the integrated circuit.

Driver circuit for capacitive display elements

A device selectively supplying a high voltage and a ground level voltage to electrodes of an electroluminescent display panel. The voltage supply device includes a first and a second transistor connected in series, and outputs the high voltage upon turning on the first switching transistor and the ground level voltage upon turning on the second switching transistor. The device includes a circuit for selecting either an operation mode under which the device is normally operated with the high voltage or a test mode under which the device is tested under a low test voltage. The mode selection is performed by an external signal supplied to the device. Under the test mode, the switching transistors are turned on with a low gate voltage by operation of a circuit built in the device. Accordingly, the voltage supply device normally operated under the high voltage is easily tested under the low test voltage.

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Nishio, Japan

Takahiro Iwamura