Sony Corporation

Takahiro Ikarashi

Satoshi Takagi

Hiroshi Sumihiro

Masao Tanaka

Yasuhiro Matsui

Yukinao Kenjo

Akihiko Saotome

A memory control circuit of the disclosure includes a memory control unit that controls a timing of command issuance to cause (tATP+tPTA) to be constant, where, in a memory having a plurality of banks, tATP is a period from issuance of a first ACT command to issuance of a PRE command that is directed a bank same as or different from a bank to which the first ACT command is issued, and tPTA is a period from the issuance of the PRE command to issuance of a second ACT command that is directed to a bank same as or different from the bank to which the PRE command is issued.

Memory control circuit and memory controlling method

A memory control circuit according to the disclosure includes a memory control section that selectively uses a first issuing mode in which a plurality of control commands are issued without performing bank group interleaving and a second issuing mode in which the bank group interleaving is performed and the plurality of control commands are issued, and thereby issues the control commands to a plurality of bank groups in a memory having a bank group function.

Memory control circuit and memory control method

The load on an arbiter that conducts arbitration among host devices is reduced in an information processing system that includes the host devices and a storage device. A memory management device includes detecting units and a command generating unit. Each of the detecting units detects a timing to execute a predetermined process for the storage device. The command generating unit generates a command common to the predetermined processes subjected to the detection in the detecting units, and a sideband signal unique to each of the predetermined signals having the execution timings detected.

Memory management device, information processing system, and method of controlling memory management device

A memory controlling device that includes a request generating section for generating a memory request, a row selecting information retaining section that retains data relative to row address information, a column selecting information retaining section that retains data relative to column address information, a memory bank information for managing section operation states of the memory device, a command generating section for generating operation commands, and a command aligning section that synchronizes the operation commands with the clock.

Memory controlling device

Disclosed herein is a memory controlling device including: an address converting section configured to convert a logical address included in a request issued from a plurality of clients into a physical address of a memory; a request dividing section configured to divide a converted request converted by the address converting section by a command unit for the memory on a basis of the physical address of the converted request; and an arbitrating section configured to perform arbitration on a basis of the physical address indicated in a divided request output from the request dividing section.

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Kanagawa, Japan

Takahiro Ikarashi