Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Socionext Inc.

Takahiro Ichinomiya

Kenji Shimazaki

Kazuhiro Sato

Sadami Takeoka

Akira Motohara

Kazuhisa Tanaka

Shouzou Hirano

Masayuki Taniyama

Takeshi Yado

Yoshinori Okajima

Hidemi Harayama

Takashi Hashimoto

Masaki Maeda

Masao Takahashi

Hiroyuki Tsujikawa

Takashi Ando

Nobufusa Iwanishi

Akio Hirata

Fumihiro Kimura

Kazuhiro Satoh

Naoki Amekawa

Masaaki Hirata

Shozo Hirano

Seijiro Kojima

A semiconductor integrated circuit, supplied with a power source voltage generated by a power supplier and having a level determined in accordance with an analog signal, includes: an output unit outputting, as the analog signal, an output voltage signal indicating the power source voltage; an input unit including an input interface identical in specifications to an output interface of the output unit, and receiving an input signal indicating a voltage and input from an outside of the semiconductor integrated circuit; and a voltage control circuit generating the output voltage signal, based on the input signal and operating voltage information indicating a voltage required for an operation of the semiconductor integrated circuit.

Semiconductor integrated circuit and power supply control system provided with a plurality of semiconductor integrated circuits

A manufacturing system which can restrain the margin of a semiconductor integrated circuit. The integrated circuit including a fixed circuit unit and a reconfigurable circuit unit outputs, to a configuration determining server, an operation time which was calculated by a detecting unit and a calculating unit. The configuration determining server, by using the operation time obtained from the integrated circuit, calculates performance data which indicates the characteristics of the fixed circuit unit, selects, based on the performance data, a piece of configuration information indicating a circuit configuration that is optimum for the processing of the reconfigurable circuit unit, and outputs the selected piece of configuration information. The integrated circuit builds a circuit in the reconfigurable circuit unit in accordance with the output piece of configuration information.

Fabrication system of semiconductor integrated circuit, fabrication device, fabrication method, integrated circuit and communication system

A semiconductor integrated circuit judges whether a power unit is performing a discharge operation or a charge operation. To reduce clock skew between a plurality of logic blocks in the semiconductor integrated circuit, when the power unit is performing the charge operation, the semiconductor integrated circuit determines a logic block that needs to be operated for the execution of a target process, as an operation block whose operation is to be started, and, determines, in the rest of the logic blocks, a logic block having a termination rate whose value is larger than a value of the minimum termination rate, as the operation block whose operation is to be started, the value of the termination rate being larger by more than a predetermined value.

Semiconductor integrated circuit, semiconductor integrated circuit control method, and terminal system

A reconfigurable computing circuit for reducing the amount of dummy data to be stored in data registers, which is required when the wiring is shared by the configuration information bus and scan chain. When data is to be stored in data registers and configuration registers constituting the scan chain in reconfig computing block, reg setting data selecting unitselects either a value stored in reg setting data storage unitor an initial value output from data reg data generating unit, based on the information stored in reg type managing unitthat indicates the types of registers and the connection order of the registers in the scan chain, and outputs the selected value in sequence to the scan chain under control of scan/reconfig control unit. Each register in the scan chain then shifts data stored therein to the next register in the scan chain in sequence.

Reconfigurable computing circuit

The number of blocks that can be stopped when performing target processing in a programmable logic unit is obtained, and a stop rate of each of a plurality of logic blocks included in the programmable logic unit is calculated. The same number of logic blocks as the blocks that can be stopped are selected from among the plurality of logic blocks in ascending order of a stop rate, the selected logic blocks are determined as logic blocks whose operations are to be stopped, and the operations are stopped. As a technique of stopping an operation of a logic block, a gated clock technique, a power-off technique, or the like is used.

Logic block control system and logic block control method

In optimizing a necessary capacitance of a semiconductor integrated circuit, the capacitance optimization can be achieved with higher precision by optimizing an IR drop (voltage drop) while considering dynamically a cell activation rate. In other words, in estimating a power-supply capacitance inserted to suppress a voltage fluctuation of the power supply, an areal demerit can be reduced by reducing a necessary capacitance component as a whole while considering a cell activation rate in the circuit or by selecting the capacitance required to supplement only temporal portions whose power-supply fluctuation is wide after the estimation of a cell operating timing. Also, the process can be conducted in a short time at the early stage of design by using a wiring load model at the time of capacitance estimate.

Method of designing a semiconductor integrated circuit

The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is inserted at least to one of the clock supply paths, which lets through the clock signals when a control signal is in a first logic state and, when the control signal is in a second logic state, outputs an inversion signal of a logic level that is outputted in a previous occasion where the control signal in the second logic state is applied.

Clock supply circuit

An impedance of a power supply wire is calculated based on design data of a semiconductor integrated circuit, a frequency characteristic of the calculated impedance is obtained, and a design of the semiconductor integrated circuit is changed based on the obtained frequency characteristic. As the above-described impedance, an impedance between power supplies that are different in potential such as a power supply and a ground may be calculated, or an impedance between power supplies that are substantially the same in potential such as a power supply and an N-well power supply may be calculated. By a design modification, a wiring method, the number of pads, separation of power supplies, a type of package, a characteristic of an inductance element, a substrate structure, a distance between wires, a decoupling capacitance, a length of a wire, and a characteristic of a resistance element, for example, are changed.

Design method for semiconductor integrated circuit suppressing power supply noise

There are contained the step of forming voltage waveform information by calculating a voltage waveform of each instance of a semiconductor integrated circuit at a power-supply terminal based on circuit information and analyzing the voltage waveform of each instance, the step of forming voltage abstraction information by abstracting the voltage waveform information, and the step of calculating a delay value of the instance based on the voltage abstraction information.

Operation analyzing method for semiconductor integrated circuit device, analyzing system used in the same, and optimization design method using the same

A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Method of designing semiconductor integrated circuit utilizing a scan test function

The layout method of a semiconductor integrated circuit device according to the present invention includes a net list modification process for adding a cell to a flip-flop group directly connected to the clock source, a process for generating gated circuit division information which allocates the division number of the gated circuit and the drive ability of the cell so that the drive ability of the cell is selected and the delay value becomes uniform, a gated circuit division process for forming a cluster by dividing each of the gated circuits through clustering, a gated cell division process for allocating to each cluster the same number of gated cells as that of the formed clusters and a gated cell front stage CTS process in order to reduce the skew of the clock signal from the clock source via the gated cell to the flip-flop and to control the power consumption of the clock signal part.

Growing community of inventors

Osaka, Japan

Takahiro Ichinomiya