Nec Corporation

Kyowa Hakko Bio Co., Ltd.

Takahiro Hara

Tadahiko Sugibayashi

Yasuji Koshikawa

Masahiko Morita

Kohji Fukunaga

Kota Kumagai

Miho Komatsu

Ryuji Yamamura

Masao Kimura

Koji Kawata

An object of the invention is to provide an agent for preventing or improving decline in brain function such as decreased perception ability, decreased memory learning ability, decreased thinking ability, decreased concentration, decreased attention, decreased judgment ability, depression, and decreased exercise performance caused thereby. According to the invention, an agent for protecting brain neuronal cells, comprising citrulline or a salt thereof and citicoline or a salt thereof as active ingredients as well as an agent for preventing or improving decline in brain function, comprising citrulline or a salt thereof and citicoline or a salt thereof as active ingredients is provided.

Agent for preventing or improving decline in brain function

An objection of the present invention is to provide an agent for preventing or improving decline in brain function such as decreased perception ability, decreased memory learning ability, decreased thinking ability, decreased concentration, decreased attention, decreased judgment ability, depression, and decreased exercise performance caused thereby. According to the present invention, an agent for protecting brain neuronal cells, comprising citrulline or a salt thereof and citicoline or a salt thereof as active ingredients as well as an agent for preventing or improving decline in brain function, comprising citrulline or a salt thereof and citicoline or a salt thereof as active ingredients is provided.

An objection of the present invention is to provide an agent for preventing or improving decline in brain function such as decreased perception ability, decreased memory learning ability, decreased thinking ability, decreased concentration, decreased attention, decreased judgment ability, depression, and decreased exercise performance caused thereby. According to the present invention, an agent for protecting brain neuronal cells, comprising citrulline or a salt thereof and glutathione or a salt thereof as active ingredients as well as an agent for preventing or improving decline in brain function, comprising citrulline or a salt thereof and glutathione or a salt thereof as active ingredients is provided.

Method of treating decline in brain function comprising coadministration of citrulline and glutathione

An agent for enhancing NO production, comprising citrulline or a salt thereof and serine or a salt thereof as an active ingredient. An agent for preventing or ameliorating vascular endothelial malfunction, comprising citrulline or a salt thereof and serine or a salt thereof as an active ingredient. An agent for preventing or ameliorating a symptom caused by vascular endothelial malfunction, comprising citrulline or a salt thereof and serine or a salt thereof as an active ingredient.

Agent for preventing deterioration in vascular endothelial function or improving vascular endothelial function

A semiconductor integrated circuit device has a first internal voltage controlling circuit which lowers an external power source voltage and produces a predetermined internal power source voltage. The device further has a second internal voltage controlling circuit formed by an internal-voltage drop detection circuit for detecting the lowering of the internal power source voltage from a predetermined reference voltage and a switching circuit for causing the external power source voltage to be directly connected to an internal voltage output terminal based on an output from the internal-voltage drop detection circuit. The internal power source voltage is maintained close to the required value thereby preventing a deterioration of circuit performance even when the external power source voltage drops close to the internal power source voltage.

Semiconductor integrated circuit device with internal voltage

A dynamic random access memory device negatively biases the semiconductor substrate, and a substrate bias system incorporated therein produces a negative bias voltage from an external power voltage level for accelerating the negative biassing operation before an internal power voltage is sufficiently developed by an internal step-down circuit incorporated therein; however, after the development, the substrate bias system produces the negative bias voltage from the internal power voltage so as to be less affectable by fluctuation of the external power voltage level.

Semiconductor integrated circuit device equipped with substrate biasing

A power supply circuit for a DRAM has a power-on detection circuit which detects when an external power supply potential reaches a predetermined potential and produces first and second detection signals, and an internal power supply circuit which generates an internal power supply potential. The power supply circuit further has a first intermediate potential generating circuit which generates a first intermediate potential from the external power supply potential and supplies it to an intermediate potential supplying node and, when the first detection signal is produced and the first intermediate potential reaches a predetermined potential, stops the supply of the first intermediate potential to the intermediate potential supplying node and the intermediate potential generating function, and a second intermediate potential generating circuit which generates a second intermediate potential from the internal power supply potential and, when the second detection signal is produced, supplies the second intermediate potential to the supplying node. The first intermediate potential generating circuit has a larger driving capability than that of the second intermediate potential generating circuit. It is made possible to shorten the rising time of the intermediate potential after the power is switched-on and to reduce the overall current consumption.

Power supply start up circuit for dynamic random access memory

A semiconductor integrated circuit device is equipped with an internal power source unit for distributing an internal power voltage level between component circuitries, and the internal power voltage level is regulated to a variable reference voltage level, wherein a first main voltage regulator regulates the variable reference voltage level to a primary reference voltage level before reaching a threshold voltage level; however, after the primary reference voltage level becomes lower than the threshold voltage level, a latching circuit supplies an activation signal to a second main voltage regulator, and the second main voltage regulator regulates the variable reference voltage level to a secondary reference voltage level so that the second main voltage regulator continuously controls the variable voltage level without any abrupt transition, thereby allowing the internal power source unit to adjust the internal power voltage level to an arbitrary point.

Semiconductor integrated circuit device having voltage regulating unit

A power-on detecting circuit produces a power-on signal upon power-on event for initializing internal component circuits, and comprises a timing generating unit for producing a timing signal when a power voltage level reaches a predetermined voltage level, a monitoring unit for producing an enable signal when a step-down power voltage level reaches a constant level, and a signal generating unit for producing the power-on signal in the concurrent presence of the enable signal and the timing signal, thereby guaranteeing the initialization of the internal component circuits.

Power-on detecting circuit desirable for integrated circuit equipped

A semiconductor integrated circuit which comprises a detection circuit for detecting a voltage of a semiconductor substrate and a negative voltage generating circuit for generating a negative voltage to be supplied to the substrate in accordance with an output signal of the detection circuit. The detection circuit includes a first P-channel MOS transistor having a gate connected to a ground potential, a source connected to a power source and a drain connected to a node coupled to the detection circuit, and a second P-channel MOS transistor having a gate connected to the substrate, a source connected to the node and a drain connected to ground. Current does not flow from the external power source to the substrate, so that, even if the negative voltage generating circuit does not have its electric current supplying capacity increased, the voltage of the substrate can be detected. A buffer circuit outputting a signal in accordance with the node voltage level, and ring oscillators switched in accordance with the signal of the buffer circuit may be used in supplying an electric current to the negative voltage generating circuit.

Semiconductor integrated circuit

A node potential V1 which is obtained by the division of an internal reference potential and a substrate potential and another node potential V2 which is obtained by the division of the internal reference potential and the ground potential are compared with each other by a current-mirror amplifier. The initial setting of the above two node potentials (V1 and V2) is made as V1&gt;V2. When the substrate potential becomes large in its absolute value, the node potential V1 falls following such change and, when it reaches a predetermined substrate potential, the potentials result in V1&lt;V2. Then, a true output node of the current-mirror amplifier outputs an output of a largely inverted output level which is further amplified by at least one inverter. The semiconductor integrated circuit device is capable of detecting the predetermined substrate potential even if there exist variations in the threshold values in MOS transistors concerned in the fabricating process.

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Tokyo, Japan

Takahiro Hara