Sharp Kabushiki Kaisha Corporation

Takahiko Yoshimoto

Shinsuke Anzai

Yasumichi Mori

Masahiko Watanabe

Takeshi Nojima

Takashi Watanabe

Munetaka Masaki

Before a signal charge from a photodiodeis transferred to a signal charge accumulating portionby a scanning circuit, a reset transistoris turned on for a prescribed period to reset the voltage of the signal charge accumulating portionin a state in which the voltage of a read signal lineis retained at a first voltage (Vg) by lowering the drain side voltage of an amplifying transistor. Subsequently, by raising the drain side voltage of the amplifying transistorby a scanning circuitto make the read signal linehave a second voltage (Vrst) higher than the first voltage (Vg), the voltage of the signal charge accumulating portionis made higher than a voltage immediately after resetting. Then, the transfer transistoris turned on to transfer the signal charge from the photodiodeto the signal charge accumulating portion

Amplification type solid-state imaging device

In a semiconductor memory device for reading out multilevel data in a time-shared manner at different timings, by providing plural control signal lines for controlling the operation timings of the output buffer circuits, the operation timings of output buffer circuits can be displaced, and the number of output buffer circuits operating simultaneously can be decreased, with the result that noise is reduced. Besides, by allowing the output buffer circuit, which outputs data read out early in a time-shared manner, to operate at an early timing, data output is terminated without retarding the operation timing of the output buffer circuit operating at the last timing.

Semiconductor memory device

Two bias circuits which supply a current to a selected memory cell and a reference memory cell have the same circuit constitution. Each bias circuit includes a first active element between a power supply node and a junction node, where a current is controlled to prevent a voltage level at the junction node from fluctuating, a second active element between the power supply node and an output node, where a current is controlled such that a voltage level at the output node is changed in direction opposite to a voltage level at the junction node in other bias circuit, a third active element and a fourth active element between the junction node and a current supply node and between the output node and the current supply node, respectively, where a bias voltage is adjusted.

Bias voltage applying circuit and semiconductor memory device

A reading circuit, for reading data from one memory cell of a plurality of memory cells, includes a plurality of division sensing circuits each connected to the one memory cell via a sensing line corresponding thereto among a plurality of sensing lines; and a current-voltage conversion circuit for converting a current flowing through each sensing line into a sensing voltage representing a potential of the corresponding sensing line. Each division sensing circuit includes a current load circuit for supplying a current to the one memory cell via a corresponding sensing line, and a sense amplifier for sensing a potential difference between the corresponding sensing line and a corresponding reference line of a plurality of reference lines. The current load circuit included in at least one division sensing circuit has a current supply capability different from that of the current load circuit included in another division sensing circuits.

Reading circuit, reference circuit, and semiconductor memory device

A synchronous semiconductor storage device which operates in synchronization with a system clock signal includes: a first feedback loop which latches an address data signal; a first latch circuit including a first transfer gate which controls the latching by the first feedback loop of the address data signal; a second feedback loop which holds the address data signal latched by the first feedback loop; a second latch circuit including a second transfer gate which controls the holding by the second feedback loop of the address data signal latched by the first feedback loop; a data input control signal generation circuit for generating a data input control signal based on the system clock signal and control signals; and an address latch signal generation circuit for generating an address latch signal from a logical sum of the system clock signal and the data input control signal, wherein the address latch signal is input to the first transfer gate to control the latching of the address data signal, and the data input control signal is input to the second transfer gate to control the holding of the address data signal latched by the first feedback loop.

Semiconductor storage device

A synchronous semiconductor storage device includes: an internal clock activation signal generation circuit for generating an internal clock activation signal cke_c and a latch signal cke based on a system clock signal CLK and a clock activation signal CKE each having a series of pulses; a CKE latch clock control signal generation circuit for generating, based on the internal clock activation signal cke_c, the latch signal cke , the system clock signal CLK, and the clock activation signal CKE, a CKE latch clock control signal cke_x which controls activation/inactivation of a CKE latch clock signal, and an internal clock signal generation circuit for generating an internal clock signal clk_in based on the internal clock activation signal cke_c and the system clock signal CLK, wherein stored data corresponding to a plurality of external signals including a control signal and an address signal are transmitted in synchronization with the internal clock signal clk_in.

Synchronous semiconductor storage device

A semiconductor memory device includes: a memory cell array including a plurality of memory cells arranged in a matrix of rows and columns; and a row selector for selecting one of the rows of the memory cell array in accordance with an input address signal, the semiconductor memory device having a burst mode for sequentially accessing one row of memory cells. The memory cell array includes a plurality of groups each including at least one column of memory cells, and wherein the semiconductor memory device further includes: a column selector for simultaneously selecting all of the columns in each group in accordance with the input address signal; and at least two precharge circuits for precharging bit lines associated with the columns in each group selected by the column selector.

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Nara, Japan

Takahiko Yoshimoto