Hitachi, Ltd.

Takahiko Takahashi

Akira Shimase

Satoshi Haraichi

Mikio Hongo

Hiroshi Yamaguchi

Fumikazu Itoh

Tateoki Miyauchi

Keiya Saito

Takashi Kamimura

Katsuro Mizukoshi

Katsuyoshi Suzuki

Junzou Azuma

Masato Hamamoto

Shigeo Kuroda

Emiko Uda

Junichi Mori

Akio Anzai

Funikazu Itoh

Shuzo Sano

Shyuzo Sano

Herein disclosed are a variety of techniques relating to the wiring and logic corrections on a chip by making use of the focused ion beam (which is shortly referred to as &ldquo;FIB&rdquo;) or the laser selection metal CVD. The time periods for the wiring corrections and for debugging and developing an electronic system are shortened by making use of the processing characteristics of the FIB. Illustratively, a hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD. The present invention also relates to an IC or VLSI structure having a trial cutting region, at test etching region and an auxiliary wiring or pad, suitable for the application of such defect correction and circuit change, as well as a method of making same, a designing method using such technique, and a focused ion beam system and other systems for use in those methods.

Method of making wiring and logic corrections on a semiconductor device by use of focused ion beams

An IC wiring connecting method for interconnecting conductive lines of the same wiring plane of an IC chip for correcting the wiring, for interconnecting conductive lines of different wiring lanes of a multilayer IC chip at the same position, or for connecting a conductive line of a lower wiring plane of a multilayer IC chip to a conductive line formed at a separate position on the same multilayer IC chip. The insulating film or films covering conductive lines to be interconnected are processed by an energy beam such as a concentrated ion beam to form holes so as to expose the respective parts of the conductive lines where the conductive lines are to be interconnected, then a metal is deposited over the surfaces of the holes and an area interconnecting the holes by irradiating the surfaces of the holes and the area by an energy beam or a concentrated ion beam in an atmosphere of a gaseous organic metal compound to form a conductive metal film electrically interconnecting the conductive lines. Also provided is an apparatus for carrying out the IC wiring connecting method, which comprises, as essential components, an ion beam material processing system, an insulating film forming system such as a laser induced CVD unit, a conductive film forming system, and an insulating film etching system.

IC wiring connecting method using focused energy beams

A processing method and apparatus using a focused energy beam for conducting local energy beam processing in a focused energy beam irradiating area by irradiating a sample with a focused energy beam such as an ion beam or an electron beam in an etching gas atmosphere. As the etching gas, a mixed gas different in composition from any conventional one is employed and the gas is uniformly supplied to an etching area and at least one of the components of such a mixed gas is a spontaneous reactive gas for use in etching the sample spontaneously and isotropically. With this arrangement, it is possible to subject to local etching a material for which the local etching has been impossible to provide since a single etching gas causes a reaction too fierce or causes almost nearly no reaction.

Processing method and apparatus using focused energy beam

IC wiring connecting method and apparatus

The wiring of a semiconductor device having a multilayer interconnection on a semiconductor substrate is modified. A plurality of fine holes are formed on an insulation film by the radiation of a converged energy beam to expose selected ones of the internal lines of the underlying wiring. A thin buffer film of Cr, Ti, TiN, or W is formed along a path where an additional connection line is to be deposited. The path extends along an upper surface of the insulating film at least in and between the said fine holes. The additional connection line is deposited on the buffer film by energy beam CVD, using Mo, W, or Al, to interconnect the exposed internal lines. The additional connection line is annealed by radiating an energy beam thereon to reduce its resistance. A further insulating film is deposited covering the additional connection line by energy beam CVD.

Method for modifying wiring of semiconductor device

A method of etching a semiconductor device having multi-layered wiring by an ion beam is disclosed which method comprises the steps of: extracting a high-intensity ion beam from a high-density ion source; focusing the extracted ion beam; causing the focused ion beam to perform a scanning operation by a voltage applied to a deflection electrode; forming a first hole in the semiconductor device by the focused ion beam to a depth capable of reaching an insulating film formed between upper and lower wiring conductors so that the first hole has a curved bottom corresponding to the undulation of the upper wiring conductor, and the upper wiring conductor is absent at the bottom of the first hole; and scanning a portion of the bottom of the first hole with the focused ion beam to form a second hole in the insulating film to a depth capable of reaching the lower wiring conductor, thereby preventing the shorting between the upper and lower wiring conductors. Further, a method of forming a hole of a predetermined shape at a surface area having a step-like portion of a semiconductor device by an ion beam is disclosed which method comprises a pre-etching step of scanning the high-level region of the step-like portion with the ion beam so that the high-level region becomes equal in level to the low-level region of the step-like portion, and a main step of scanning the whole of the surface area with the ion beam till the hole of the predetermined shape is formed in the semiconductor device.

Method of etching a semiconductor device by an ion beam

In locally reactive etching by irradiating to a multilayered workpiece reactive beam generated by extracting the reactant gas ionized or by irradiating such focussing beam as ion beam, electron beam or laser beam to the multilayered workpiece in an atmosphere of reactant gas; each layer of a multilayered device comprising a plurality of layers formed on a substrate can be accurately and quickly eteched by detecting the change of the material of the layer currently being etched and after detecting the change of material, switching reactant gas to be ionized or atmospheric reactant gas to one complying with the material of the layer currently being etched. This multilayered device micro etching method can be readily put into practice by a multilayered device micro etching system further comprising means for detecting the change of the material of layer to be etched and means for switching and supplying a plurality of reactant gases, in a micro etching appratus for performing locally rective etching.

Multilayered device micro etching method and system

A wiring method for on-chip modification of an LSI is provided to cut a portion of a wire inside of the LSI with an ion beam and connect the wire with a laser induced CVD process so that the logic is changed when developing the LSI. The method comprises the steps of cutting or connecting an LSI wire even if another wire is located above or adjacent to the LSI wire and repairing an excessively cut or connected portion. The method thus makes it possible to widen the range of a possible cutting or connection spot, thereby making any kind of repairs possible, some of which would have never been repaired by the conventional method.

Wiring method of on-chip modification for an LSI

A semiconductor IC device having a substrate, a patterned conductor layer for interconnection of regions in the substrate and a passivation layer covering the device is provided with an additional conduction path of a pattern and/or part of the patterned conductor layer is removed for disconnection for the purpose of evaluation of the characteristics of the device. The additional conduction path is formed by forming a hole in the passivation layer to expose a part of the conductor layer, directing, in an atmosphere containing a metal compound gas, an ion beam onto the hole and onto a predetermined portion of the passivation layer on which the additional conduction path of a pattern is to be formed to thereby form a patterned film of the metal decomposed from the metal compound gas and forming an additional conductor on the patterned film. The provision of the additional conduction path and/or the removal of part of the patterned conductor layer is preformed in a chemical vapor deposition apparatus which includes a vacuum chamber and an ion beam radiation unit having a housing partitioned into, for example, first, second and third compartments. The ion beam radiation unit has an ion source placed in the first compartment, an ion beam focusing and deflecting device placed in the second compartment and pressure buffer constituted by the third compartment. The third compartment is coupled to and pneumatically isolated from the vacuum chamber for conducting an ion beam emitted from the ion source, passing the second compartment and ejected from the second compartment to the vacuum chamber.

Method of providing a semiconductor IC device with an additional

The present invention relates to a semiconductor integrated circuit device and a process for producing the same. A hole is bored in an insulating film above a portion of a wiring which is to be connected to another wiring by means of a focused ion beam. The inside of the hole and a predetermined region on the insulating film are irradiated with either a laser beam or an ion beam in a metal compound gas to deposit metal in the hole and on said region and a connecting wiring is formed by means of optically pumped CVD. To electrically connect upper- and lower-level wirings in a multilayer wiring structure by a connecting wiring, the connecting wiring is electrically isolated from an intermediate-level wiring through which it extends. The above-described arrangement enables provision of a hole with a focused ion beam and formation of a metal wiring on a selective region by means, for example, optically pumped CVD. Accordingly, it is possible to effect fine machining and electrically connect together wirings inside an LSI after the completion thereof. It is therefore possible to carry out debugging, repair and a defect analysis of the LSI.

Semiconductor integrated circuit device and process for producing the

A IC wiring connecting method for interconnecting conductive lines of the same wiring plane of an IC chip for correcting the wiring, for interconnecting conductive lines of different wiring lanes of a multilayer IC chip at the same position, or for connecting a conductive line of a lower wiring plane of a multilayer IC chip to a conductive line formed at a separate position on the same multilayer IC chip. The insulating film or films covering conductive lines to be interconnected are processed by an energy beam such as a concentrated ion beam to form holes so as to expose the respective parts of the conductive lines where the conductive lines are to be interconnected, then a metal is deposited over the surfaces of the holes and an area interconnecting the holes by irradiating the surfaces of the holes and the area by an energy beam or a concentrated ion beam in an atmosphere of a gaseous organic metal compound to form a conductive metal film electrically interconnecting the conductive lines. Also provided is an apparatus for carrying out the IC wiring connecting method, which comprises, as essential components, an ion beam material processing system, an insulating film forming system such as a laser induced CVD unit, a conductive film forming system, and an insulating film etching system.

IC wiring connecting method and resulting article

A method of fabricating semiconductor integrated circuit devices having a semiconductor region in a position separated by a predetermined distance from a dielectric isolating region provided on the surface of a semiconductor wafer, comprising the steps of forming a first mask to define the dielectric isolating region and semiconductor region, forming a second mask over the first mask so as to cover the region which is to become the semiconductor region, and removing the second mask after the dielectric isolating region has been formed by the first and second masks, to form the semiconductor region. The method thus permits the semiconductor region to be self-aligned with the dielectric isolating region.

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Iruma, Japan

Takahiko Takahashi