Fujitsu Semiconductor Limited

Fujitsu Corporation

Windbond Electronics Corp.

Winbond Electronics Corporation

Fujitsu Microelectronics Limited

Takahiko Sato

Tatsuya Kanda

Hitoshi Ikeda

Toshiya Uchida

Tatsushi Otsuka

Shinnosuke Kamata

Ayako Sato

Tetsuo Miyamoto

Hidenaga Takahashi

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Akihiro Funyu

Hiroyuki Kobayashi

Naoharu Shinozaki

Tomohiro Kawakubo

Yoshiaki Okuyama

Jun Ohno

A pseudo-static random access memory is provided herein, which may improve the speed of data transmission. After a first delay from a command and a row address being input in a first operation, the pseudo-static random access memory inputs or outputs the data in the memory cells corresponding to the input row address and the input column address, which includes a control unit controlling a delay in the second operation less than the initial delay when a specific condition is satisfied. The second operation is executed after the first operation.

Pseudo-static random access memory

A voltage generation circuit and a semiconductor memory device capable of decreasing the layout size and the consumed current are provided. A voltage generation circuit includes a plurality of voltage generation units which generate different output voltages based on an external power supply voltage. Each of the plurality of voltage generation unit comprises a plurality of resistors that are connected in series to detect the output voltages. At least one of these resistors is coupled to and shared by the plurality of voltage generation units.

Voltage generation circuit for memory device with series connected resistors

The present invention provides a memory system in which a semiconductor memory device can be accessed properly. The memory system includes a memory controller and a semiconductor memory device. The memory controller sends a command, an address, and first checking data to the semiconductor memory device. When the semiconductor memory device receives first response information that indicates that no error has been detected, it sends or receives read data or write data from the semiconductor memory device. When the semiconductor memory device receives the command, the address, and the first checking data, it uses the first checking data to detect errors in the command and the address, and sends the first reply information when no error is detected, and when no error is detected in the command and the address, it sends or receives read data or write data from the semiconductor memory device.

Memory system

A semiconductor memory device is provided to suppress occurrence of disturbance regardless of the position of the activated word line. The semiconductor memory device includes a plurality of word lines, a bit line, a plurality of memory cells connected to the bit line and one of the plurality of word lines, a sense amplifier connected to the bit line, and a control portion. The control portion is configured to control timing of activating the sense amplifier. When a position of an activated word line among the plurality of word lines is closer to the sense amplifier, the control portion controls the timing of activating the sense amplifier to be delayed more.

Sense amplifier activation timing scheme to suppress disturbance in memory cells of dram memory device

A semiconductor memory device is provided. The semiconductor memory device can suppress increases in power consumption. As a result, damage to the data normally caused by row hammer problem can be prevented. The semiconductor memory device includes a control unit. The control unit controls a refresh operation for a memory to be performed at any interval, wherein there are a plurality of possible intervals. When read/write access to the memory is required, the control unit controls the refresh operation for the memory to be performed with a shortest interval among the intervals, until a predetermined condition is met.

Semiconductor memory device

A temperature sensing circuit adapted for a memory device and including an oscillator, a count circuit, a control circuit, a sense circuit and a select circuit is provided. The oscillator provides an oscillation signal. The count circuit counts the oscillation signal to generate a first count signal, and generates a second count signal. The count circuit performs a logic operation on the second count signal to generate an enable signal and a sensing adjustment signal. The sense circuit generates a reference temperature voltage by dividing a reference voltage according to the sensing adjustment signal, and compares the reference temperature voltage and a monitor voltage according to the enable signal to generate a determination signal. The select circuit dynamically selects one of the oscillation signal and the first count signal according to the determination signal, and generates a pulse of a refresh request signal according to the dynamically selected one of the oscillation signal and the first count signal.

Temperature sensing circuit and sensing method thereof

A power supply control circuit that is able to reliably discharge to the internal power supply, even when the external power supply is cut off instantaneously. The power supply control circuit includes a voltage detection unit, an internal power supply generation unit, and a control unit. The voltage detection unit detects the voltage of the external power supply. The internal power supply generation unit generates the internal power supply, according to the external power supply. The control unit controls the discharging to the internal power supply according to at least the second control signal among the first control signal and the second control signal, when the detected voltage of the external power supply drops below the predetermined value.

Power supply control circuit

A radio communication processor receives first received data including first write data, a first address within a first area of a nonvolatile memory, and error detection information or second received data including second write data whose data amount is larger than a data amount of the first write data and a second address within a second area of the nonvolatile memory. If the radio communication processor receives the first received data, then a controller stores the first write data in a volatile buffer. If there is no error in the first write data, then the controller reads out the first write data from the volatile buffer and stores the first write data in the first area. If the radio communication processor receives the second received data, then the controller stores the second write data in the second area without storing the second write data in the volatile buffer.

Semiconductor memory having radio communication function and write control method

The disclosure provides a voltage generator including a first voltage regulator which provides an output voltage to an output terminal according to a reference voltage; a second voltage regulator which determines whether to operate in an enable mode or a disable mode according to an enable signal and provides the output voltage to the output terminal according to the reference voltage when operating in the enable mode; an initial voltage generator which sets a feedback voltage of the second voltage regulator to be an initial voltage value close to the reference voltage when the enable signal switches the second voltage regulator from the disable mode to the enable mode, such that the feedback voltage of the second voltage regulator is able to be locked to the reference voltage fast, and a settling time and an overshoot/undershoot of the output voltage are reduced.

Voltage generator

A radio communication processor receives data to which identification information is assigned and transmits a response signal indicative of whether or not application processing based on the data is normally performed. An application controller controls the application processing on the basis of the data and detects whether or not the application processing is normally performed. A controller detects on the basis of the identification information that the same data are received in succession due to retransmission, nullifies, when the application controller detects that the application processing based on the data received earlier is normally performed, control of the application processing based on the data received later to be performed by the application controller and instructs the radio communication processor to transmit the response signal which indicates that the application processing is normally performed.

Semiconductor memory having radio communication function and application control method

A memory has memory cells in a matrix; a first selection unit selecting any of first signal lines in the memory cells, in response to an access request; a second selection unit selecting any of second signal lines in the memory cells, after the first selection unit starts operating; a first voltage generation unit generating a first power supply voltage supplied to the first selection unit; a second voltage generation unit generating a second power supply voltage supplied to the second selection unit, when a start-up signal is active; a switch short-circuiting first and second power supply lines, when a short-circuit signal is active; and a power supply voltage control unit which activates the start-up signal in response to the access request, activates the short-circuit signal after a predetermined time elapses since activation of the start-up signal, deactivates the short-circuit signal and the start-up signal after completion of access operations.

Semiconductor memory, system, and method of operating semiconductor memory

An internal voltage generation circuit includes a vblh voltage generation circuit that generates a voltage vblh that is supplied as a high-voltage power supply of a sense amplifier, and a voltage distribution control circuit that has a first current source that pulls down an output node and a second current source that pulls up the output node. The output node is pulled down by the first current source operating, and the voltage thereof is maintained at a voltage that corresponds to a lower limit of a detection voltage value. The output node is pulled up by the second current source operating, and the voltage thereof is maintained at a voltage that corresponds to an upper limit of the detection voltage value.

Internal voltage generation circuit of semiconductor memory device, and semiconductor memory device

A memory device includes: a memory cell array which stores two-dimensionally arranged data in a plurality of memory unit regions selected by an address; an internal address control unit which generates an internal address which selects a memory unit region according to an external address; and a decoder which decodes the internal address and selects a memory unit region. The plurality of memory unit regions store data arranged in a first direction from among two-dimensionally arranged data according to a least-significant bit group of the internal address and store data arranged in a second direction from among the two-dimensionally arranged data according to a most-significant bit group of the address. The internal address control unit successively generates an internal address corresponding to the scan direction according to a scan direction control signal which controls a plurality of scan directions including at least an oblique direction of the two-dimensionally arranged data.

Memory device and memory control for controlling the same

A semiconductor memory device comprises: a memory cell group, the memory cell including a number of which is 2n, the n being a positive integer; and a first decoder provided with respect to each of the memory cell groups and a second decoder. The first decoder activates a word line by the memory cell group based upon a first address and an n bit in a second address and the second decoder activates a bit line based upon the second address.

Semiconductor memory device, image processing system, and image processing method

A semiconductor device includes a first input circuit to which a first supply voltage is supplied, a second input circuit to which a second supply voltage that is lower than the first supply voltage is supplied, and a control circuit which activates the first input circuit in a first mode and activates the second input circuit in a second mode. The control circuit controls the first input circuit and the second input circuit such that the first input circuit and the second input circuit are activated during a certain time period when switching between the first mode and the second mode.

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Kawasaki, Japan

Takahiko Sato