Semiconductor Energy Laboratory Co., Ltd.

Takahiko Ishizu

Tatsuya Onuki

Kiyoshi Kato

Shunpei Yamazaki

Shuhei Nagatsuka

Takanori Matsuzaki

Hiroki Inoue

Wataru Uesugi

Takayuki Ikeda

Yuki Okamoto

Kazuma Furutani

Kei Takahashi

Yutaka Shionoiri

Hikaru Tamura

Atsushi Miyaguchi

Minato Ito

Atsuo Isobe

Toshihiko Saito

Seiichi Yoneda

Yuto Yakubo

Hideki Uochi

Tomoaki Atsumi

Munehiro Kozuma

Takeshi Aoki

Masashi Fujita

Naoaki Tsutsui

Hidetomo Kobayashi

Takuro Ohmaru

Yusuke Negoro

Kousuke Sasaki

Keita Sato

A semiconductor device with a novel structure is provided. The semiconductor device includes a memory circuit including a first transistor and a second transistor. The first transistor is formed on a silicon substrate. The second transistor is formed in a layer above a layer where the first transistor is provided. The first transistor includes a first gate electrode and a first back gate electrode with a first channel formation region interposed therebetween. The first gate electrode is electrically connected to one of a source and a drain of the second transistor. The first back gate electrode is formed using a region where an impurity element imparting a conductivity type is selectively introduced in the silicon substrate. The second transistor includes a second channel formation region. The second channel formation region includes a metal oxide.

Semiconductor device

A semiconductor device having a novel structure is provided. The semiconductor device includes a p-channel transistor and an n-channel transistor provided over a silicon substrate. One of a source and a drain of the p-channel transistor is electrically connected to a first power supply line, one of a source and a drain of the n-channel transistor is electrically connected to a second power supply line, and the other of the source and the drain of the p-channel transistor is connected to the other of the source and the drain of the n-channel transistor. The p-channel transistor includes a first gate electrode and a first back gate electrode provided to face the first gate electrode with a first channel formation region therebetween. The first back gate electrode is formed using a region where an impurity element imparting conductivity is selectively introduced to the silicon substrate. The n-channel transistor is provided above a layer including the p-channel transistor.

To provide a battery control circuit with a novel structure, a battery protection circuit with a novel structure, and a power storage device including the battery circuit. The semiconductor device includes n cell-balance circuits (n is an integer greater than or equal to 1). One secondary battery is electrically connected to one cell-balance circuit. The cell-balance circuit includes a comparison circuit, and a memory element is electrically connected to an inverting input terminal of the comparison circuit. The memory element includes a first transistor and a capacitor. A potential is retained. The retained potential changes in accordance with a change in a potential of a negative electrode of the secondary battery. The comparison circuit has a function of comparing the retained potential with a potential of a positive electrode of the secondary battery. Output from the comparison circuit controls a gate voltage of a second transistor electrically connected to the secondary battery in parallel. The first transistor includes a metal oxide including indium in a channel formation region.

Semiconductor device and operating method of semiconductor device

A memory device with shortened access time in data reading is provided. The memory device includes a first layer and a second layer positioned above the first layer, the first layer includes a reading circuit, and the second layer includes a first memory cell and a second memory cell. The reading circuit includes a Si transistor. The first memory cell and the second memory cell each include an OS transistor. The first memory cell is electrically connected to the reading circuit, and the second memory cell is electrically connected to the reading circuit. When a first current corresponding to first data retained in the first memory cell flows from the reading circuit to the first memory cell and a second current corresponding to second data retained in the second memory cell flows from the reading circuit to the second memory cell, the reading circuit compares the current amounts of the first current and the second current, and reads the first data.

Memory device, semiconductor device, and electronic device

A semiconductor device capable of stable operation with low power consumption is provided. A logic circuit having a circuit configuration using a transistor including an oxide semiconductor in a channel formation region is included. The logic circuit is a two-input/two-output two-wire logic circuit. Transistors included in the logic circuit each include a gate and a back gate. An input terminal is electrically connected to one of a gate and a back gate of a transistor electrically connected to a wiring for supplying a high power supply potential. An output terminal is connected to the other of the gate and the back gate of the transistor electrically connected to the wiring for supplying a high power supply potential. An output terminal is electrically connected to one of a source and a drain of a transistor electrically connected to a wiring for supplying a low power supply potential. A gate or a back gate of the transistor electrically connected to the wiring for supplying a low power supply potential is electrically connected to an input terminal.

A memory device having long data retention time and high reliability is provided. The memory device includes a driver circuit and a plurality of memory cells, the memory cell includes a transistor and a capacitor, and the transistor includes a metal oxide in a channel formation region. The transistor includes a first gate and a second gate, and in a period during which the memory cell retains data, negative potentials are applied to the first gate and the second gate of the transistor.

Memory device and electronic device

An arithmetic device and an electronic device having small power consumption is provided. An arithmetic device and an electronic device capable of high-speed operation is provided. An arithmetic device and an electronic device capable of suppressing heat generation is provided. The arithmetic device includes a first arithmetic portion and a second arithmetic portion. The first arithmetic portion includes a first CPU core and a second CPU core. The second arithmetic portion includes a first GPU core and a second GPU core. The CPU cores each have a power gating function and each include a first data retention circuit electrically connected to a flip-flop. The first GPU core includes a second data retention circuit capable of retaining an analog value and reading out the analog value as digital data of two or more bits. The second GPU core includes a third data retention circuit capable of retaining a digital value and reading out the digital value as digital data of one bit. The first to third data retention circuits each include a transistor including an oxide semiconductor and a capacitor.

Arithmetic device and electronic device

A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

A semiconductor device with reduced power consumption is provided. The semiconductor device includes a node ND, a node ND, a resistor, a capacitor, and a comparison circuit. The resistor is electrically connected in series between one of a positive electrode and a negative electrode of a secondary battery and a first terminal. The resistor has a function of converting current flowing between the one of the positive electrode and the negative electrode of the secondary battery and the first terminal into a first voltage. The first voltage is added to a voltage of the node NDthrough the capacitor. The comparison circuit has a function of comparing a voltage of the node NDand the voltage of the node ND. The comparison circuit outputs a signal that notifies detection of overcurrent when the voltage of the node NDis higher than the voltage of the node ND

Semiconductor device and battery pack

A memory device which includes a gain-cell memory cell formed using an n-channel transistor and in which a potential lower than a potential applied to a bit line is not necessary is provided. Memory cells included in the memory device are arranged in a matrix, and each of the memory cells is connected to a write word line, a write bit line, a read word line, and a read bit line. The write word line is arranged in parallel to one of directions of a row and a column of memory cells arranged in a matrix, and the write bit line is arranged in parallel to the other of the directions of the row and the column. The read word line is arranged in parallel to the one of the directions of the row and the column of the memory cells arranged in a matrix, and the read bit line is arranged in parallel to the other of the directions of the row and the column.

A battery control circuit having a novel structure, a battery protection circuit having a novel structure, and a power storage device including the battery circuit are provided. A semiconductor device includes n cell balancing circuits that respectively correspond to one secondary battery and each include a transistor, a comparator circuit, and a capacitor. In each of the n cell balancing circuits, an inverting input terminal of the comparator circuit and one electrode of the capacitor are electrically connected to one of a source and a drain of the transistor. The semiconductor device has functions of supplying a ground potential to the other electrode of the capacitor; turning on the transistor; supplying a first potential to the one electrode of the capacitor; turning off the transistor; electrically connecting the other electrode of the capacitor and a negative electrode of the secondary battery corresponding to each cell balancing circuit; supplying a sum of the first potential and a potential of the negative electrode of the secondary battery corresponding to each cell balancing circuit, to the one electrode of the capacitor; and controlling charging of the secondary battery corresponding to each cell balancing circuit.

A semiconductor device in which energy required for data transfer between an arithmetic device and a memory is reduced is provided. The semiconductor device includes a peripheral circuit and a memory cell array. The peripheral circuit has a function of a driver circuit and a control circuit for the memory cell array, and an arithmetic function. The peripheral circuit includes a sense amplifier circuit and an arithmetic circuit, and the memory cell array includes a memory cell and a bit line. The sense amplifier circuit has a function of determining whether the bit line is at a high level or a low level, and outputs the result to the arithmetic circuit. The arithmetic circuit has a function of performing a product-sum operation, the result of which is output from the semiconductor device.

Semiconductor device comprising memory cell array and arithmetic circuit

A semiconductor device capable of detecting a micro-short circuit of a secondary battery is provided. The semiconductor device includes a first source follower, a second source follower, a transistor, a capacitor, and a comparator. A negative electrode potential and a positive electrode potential of the secondary battery are supplied to the semiconductor device, a first potential is input to the first source follower, and a second potential is input to the second source follower. A signal for controlling the conduction state of the transistor is input to a gate of the transistor, and an output potential of the first source follower related to the potential between the positive electrode and the negative electrode of the secondary battery is sampled. The comparator compares the sampled potential with an output potential of the second source follower, whereby the semiconductor device can deal with a secondary battery in which the potential between the positive electrode and the negative electrode is changed by charge and discharge.

Device detecting abnormality of secondary battery and semiconductor device

An imaging device having a motion detecting function and an image processing function is provided. The imaging device can detect a difference between a reference frame image and a comparative frame image, and can switch from a motion detecting mode to a normal image capturing mode when a significant difference is detected. A low-frame-rate operation in the motion detecting mode can reduce power consumption. Moreover, the imaging device has an image recognition function in combination with the motion detecting function, so that switching from the motion detecting mode to the normal image capturing mode can be performed when a particular image is recognized.

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Kanagawa, Japan

Takahiko Ishizu