Kabushiki Kaisha Toshiba

Kioxia Corporation

Kabuhsiki Kaisha Toshiba

Takahiko Hara

Hiroshi Maejima

Masaru Koyanagi

Mitsuhiro Noguchi

Koichi Fukuda

Minori Kajimoto

Kaoru Nakagawa

Satoru Takase

Syuso Fujii

Kosuke Yanagidaira

Toshiki Hisada

Natsuki Kushiyama

Katsuki Matsudera

Kazuhide Yoneya

Takumi Abe

Takashi Maeda

Takeshi Nagai

Masahiro Yoshihara

Shigeyoshi Watanabe

Mikihiko Ito

Rieko Funatsuki

Midori Morooka

Tohru Kimura

A semiconductor storage apparatus includes a memory cell array including a plurality of memory string structures each including a pair of memory string formation sections each formed by a channel formation film and a charge storage film and including a select gate transistor and a plurality of memory cell transistors connected in series and a partial conductive layer configured to electrically connect the memory string formation sections. During a reading operation of a memory cell transistor, at least one of the plurality of memory cell transistors and the select gate transistor belonging to the memory string formation section is turned off such that a channel of a memory cell transistor is fixed to a potential of a source line or a potential of bit lines.

Semiconductor storage apparatus including a memory cell array

A nonvolatile semiconductor memory according to the present invention includes memory cell units, which include data select lines formed in parallel to each other, data transfer lines crossing the data select lines and aligned in parallel to each other, and electrically rewritable memory cell transistors disposed at intersections of the data transfer lines and the data select lines. It further includes: a memory cell array block in which the memory cell units are disposed along the data select lines; first source lines, connected to one end of the memory cell units, and aligned along the data select lines; and second source lines electrically connected to the first source lines, and disposed along the data select lines.

Nonvolatile semiconductor memory

A semiconductor device includes a plurality of semiconductor chips and a memory device. The semiconductor chips are provided in a package. Each of the semiconductor chips includes a memory cell array having memory cells which stores data, an output buffer which outputs data read from the memory cell array to an exterior of the semiconductor chip and a control circuit which controls driving power of the output buffer. The memory device stores the number of semiconductor chips provided in the package. The control circuit controls the driving power according to the number of semiconductor chips stored in the memory device.

Memory circuit system having semiconductor devices and a memory

A semiconductor integrated circuit device includes a semiconductor chip, a memory cell array arranged on the semiconductor chip and first and second decoder strings arranged along both ends of the memory cell array. The arrangement position of the first decoder string is deviated from the arrangement position of the second decoder string and a space caused by the deviation is arranged in the corner of the semiconductor chip.

Semiconductor intergrated circuit device

A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an advance-write voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the advance-write voltage is less than the reference pulse number of the advance-write voltage, the voltage generating circuit in a manner to decrease at least an initial value of a write voltage and a step-up width of the write voltage in accordance with the parameter.

Semiconductor memory device and control method of the same

A NAND-structured flash memory including a selection transistor having a first conducting path, one end of the first conducting path being connected to a bit line or a source line, at least one dummy gate having a second conducting path and a control gate, one end of the second conducting path being connected to the other end of the first conducting path of the selection transistor, a nonvolatile memory linked unit for storing external data, which includes a plurality of electrically erasable/writable nonvolatile memory cells having third conducting paths and control gates, the third conducting paths being connected in series, one end of the series of the third conducting paths being connected to the other end of the second conducting path of the dummy gate, a dummy gate driving circuit controlling a potential of the control gate of the dummy gate, and a memory cell driving circuit selectively driving the control gates of the plurality of nonvolatile memory cells to write, read or erase bit data for storing the external data.

Nand-structured flash memory

A semiconductor memory device includes a memory cell array, a voltage generating circuit, a memory circuit which stores a reference pulse number of an erase voltage of the memory cell array and a parameter, and a control circuit which controls, when a pulse number of the erase voltage exceeds the reference pulse number of the erase voltage, the voltage generating circuit in a manner to increase at least an erase verify level in accordance with the parameter.

Semiconductor integrated circuit device

A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.

NAND-structured flash memory

A non-volatile semiconductor memory device includes a cell array in which electrically rewritable and non-volatile memory cells are arranged, and a sense amplifier circuit configured to read and write data in association with the cell array, wherein the sense amplifier circuit includes: differential amplifier having first and second input nodes and configured to amplify a difference voltage between the first and second input nodes; a data transfer circuit configured to selectively connect the first input node to a bit line in the cell array; a reference voltage setting circuit configured to apply a reference voltage to the second input node of the differential amplifier; and a data storing circuit configured to temporarily hold a loaded write data at the first input node of the differential amplifier, and control the reference voltage at the second input node of the differential amplifier in correspondence with the write data held therein.

Non-volatile semiconductor memory device and electric device with the same

A semiconductor integrated circuit is composed of a memory array, sense amplifiers, a first and second drive circuits, and a sense amplifier control circuit. The memory cell array has memory cells arranged in matrix form. The sense amplifiers amplify a signal read from the memory cells. The sense amplifiers include N channel sense amplifiers each composed of an N channel MOS transistor and P channel sense amplifiers each composed of a P channel MOS transistor. The first and second drive circuits each include an N channel MOS transistor that drives the N channel sense amplifiers or the P channel sense amplifiers, respectively. The first and second drive circuits are arranged adjacent to the sense amplifiers. The sense amplifier control circuit supplies a common control signal to both gate electrodes of the N channel MOS transistors included in the first and second drive circuits.

Semiconductor integrated circuit comprising sense amplifier activating circuit for activating sense amplifier circuit

A semiconductor integrated circuit includes a control data storage circuit ( ) having nonvolatile storage devices with programmed control data and a latch circuit for holding data read out from the storage devices, and a read control circuit ( ) for controlling read operations of the control data, which are built in a semiconductor chip. The control data storage circuit ( ) is divided into groups ( ), and the read control circuit ( ) generates read control signals for the groups ( ) at different timings, using an output of an internal potential detecting circuit as the timing reference, thereby preventing the peak of power consumption from unacceptably rising during reading operations.

Growing community of inventors

Yokohama, Japan

Takahiko Hara