Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Takahiko Fukiage

Susumu Tanida

Mikio Sakurai

Shinji Tanaka

Yasuhiro Konishi

Seiji Sawada

Yasuhiko Tsukikawa

Yoshinori Inoue

Yasuhiro Matsumoto

Masaya Nakano

In a semiconductor memory device including a plurality of memory chips, the plurality of memory chips are divided into first and second groups that are operated in parallel with each other at the time of a data read. Timings of activating sense amplifiers belonging to the first and second groups are made different from each other. Accordingly, the maximum value of peak current generated when the sense amplifiers are activated at the time of a data read is reduced by half in the semiconductor memory device as a whole. As the peak current is suppressed, the data reading operation can be executed stably.

Semiconductor memory device suppressing peak current

A bare chip is provided with a pad for activation/deactivation control to which a deactivation control signal for converting a bare chip that has been detected as being defective into the deactivated condition is inputted. When a deactivation control signal is inputted to the pad for activation/deactivation control, internal circuit prevent a signal that has been inputted from the pad for data input/output control from being inputted to an internal circuit located further inside than the input buffer circuit. Thereby, the bare chip that has been detected as being defective can be converted to the deactivated condition. As a result, a semiconductor memory module can be obtained that can be repaired by newly mounting a good function chip without allowing the bare chip that has been detected as being defective to interfere with the functions of the semiconductor memory module.

Semiconductor memory module

A reset signal generating circuit in a synchronous semiconductor memory device outputs a reset signal ZPOR1 in response to a power on reset signal ZPOR generated immediately after power on and an initialize command (for example, a precharge command) executed for initialization after power on. A test mode register included in a mode setting circuit receives as a reset signal, the reset signal ZPOR1. Consequently, a test mode signal output attains to an NOP state, or output of the test mode signal is stopped.

Synchronous semiconductor device having circuitry capable of surely

A read register and a data transfer circuit are provided to implement two separate data transfer paths with respect to a preamplifier, for alternately transferring data through these two paths. Thus, the data can be transferred with no data collision in each clock cycle. The data are transferred at a high speed every clock cycle regardless of the bank number and the CAS latency in a multi-bank synchronous memory device.

Multi-bank synchronous semiconductor memory device

A dynamic type semiconductor memory device includes a plurality of data input/output nodes, a plurality of /CAS buffers for generating column address strobe signals corresponding to each of said input/output nodes, and an input node carrying out only data input. A switching signal generation circuit generates first and second switching signals indicating data input/output control modes. Memory cells corresponding in number to the data input/output nodes are selected simultaneously from a memory cell array. In operation of control mode A, data input/output is effected using an input node and one data input/ouput node. In the case of control mode B, data writing/reading is effected via a plurality of data input/output nodes according to one column address strobe signal. In the case of control mode C, data input/output is carried out individually for each input/output node according to a plurality of column address strobe signals. Modes A, B and C can be realized in one DRAM. Particularly, in mode C controlling data input/output according to respective column address strobe signals, writing/reading of unnecessary data bits can be prevented to reduce power consumption and prevent erroneous parity bit writing.

Semiconductor memory device with changeable input/output data bit

In an output stage, an n-FET and a p-FET are connected in series, which is interposed between a power supply line and a ground. A first serial connection circuit generates a gate potential of the n-FET, and a second serial connection circuit generates a gate potential of the p-FET. The first and the second serial connection circuits are connected in parallel to each other, each of which has its one end connected to the power supply line through a resistor, and its other end connected to the ground through a resistor. As a result, even if a resistance value of the resistor is small, currents to be consumed can be reduced.

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Hyogo, Japan

Takahiko Fukiage