Fujitsu Corporation

Takahide Yoshikawa

Shiho Nakahara

Hiroyoshi Kodama

Tsuneo Nakata

Yuzi Kanazawa

A non-transitory computer-readable recording medium stores a conversion program for causing a computer to execute a process including: dividing a source program into a plurality of program blocks; selecting, based on a result of analysis of an access count from each of the plurality of program blocks to each of a plurality of accelerators, a first program block among the plurality of program blocks and an accelerator of an arrangement destination of the first program block, among the plurality of accelerators; and converting the first program block into a hardware logic to be operated in the accelerator of the arrangement destination.

Computer-readable recording medium storing conversion program and conversion processing method

A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

Semiconductor device and method for controlling semiconductor device

A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Information processing device and information processing method for prefetching across page boundaries

Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

Semiconductor circuit design support technique

A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

Growing community of inventors

Kawasaki, Japan

Takahide Yoshikawa