Terarecon, Inc.

Mitsubishi Electric Information Technology Center America, Inc.

E Ink Corporation

Seiko Epson Corporation

Quickturn Design Systems, Inc.

Takahide Ohkami

Hugh C Lauer

Hanspeter Pfister

James M Knittel

Christopher J Kappler

Jan C Hardenbergh

William R Peet

Stephen R Burgess

Holly G Gates

Yun Shon Low

John Peter Van Baarsen

Kenneth W Correll

Jay C Wilkinson

Stephen F Mason

Beverly J Schultz

Masato Ogata

A method for updating two or more regions of the display area of a bistable, electro-optic display device comprises selecting at least one first waveform for at least one pixel of a first region; (b) selecting at least one second waveform for at least one pixel of a second region; (c) updating the first region by generating and providing the first waveform to the at least one pixel of the first region; and (d) updating the second region by generating and providing the second waveform to the at least one pixel of the second region, wherein the first and second updates at least partially coincide in time. The first waveform is selected from a first drive scheme for use in a first update mode having a first period. The second waveform is selected from second a drive scheme for use in a second update mode having a second period.

Time-overlapping partial-panel updating of a bistable electro-optic display

A data structure for use in controlling a bistable electro-optic display having a plurality of pixels comprises a pixel data storage area storing, for each pixel of the display, data representing initial and desired final states of the pixel, and a drive scheme index number representing the drive scheme to be applied; and a drive scheme storage area storing data representing at least all the drive schemes denoted by the drive scheme index numbers stored in the pixel data storage area. A corresponding method of driving a bistable electro-optic display using such a data structure is also provided.

Methods for driving electro-optic displays

A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Hardware-assisted design verification system using a packet-based protocol logic synthesized for efficient data loading and unloading

A plurality of identical rendering pipelines are connected in parallel to read an array of voxels and to write an array of pixels. Each pipeline processes one voxel in one processing cycle of the pipelines. Each pipeline includes a plurality of serially connected different stages. The stages can include interpolation, classification, gradient estimation, illumination, and compositing stages. Interfaces connect identical stages in adjacent pipelines as one-way rings to communicate information associated with spatially adjacent voxels, and delay buffers connected parallel to particular stages communicate information associated with temporally adjacent voxels.

Volume rendering pipeline

A volume rendering integrated circuit includes a plurality of interconnected pipelines having stages operating in parallel. The stages of the pipelines are interconnected in a ring, with data being passed in only one direction around the ring. The volume integrated circuit also includes a render controller for controlling the flow of volume data to and from the pipelines and for controlling rendering operations of the pipelines. The integrated circuit may further include interfaces for coupling the integrated circuit to various storage devices and to a host computer.

Volume rendering integrated circuit

A volume rendering system re-samples voxels read from a voxel memory to generate samples along perspective rays cast from a center of projection using a level of detail value. Color computations are performed with the samples to produce pixels for a baseplane image. The level of detail is computed, at each plane of samples perpendicular to a principal viewing axis, from the current sample position and the distance between the center of projection and the baseplane; the principal viewing axis is the coordinate axis in a rendered volume most parallel with a viewing vector. The level of detail provides a measure of the distance between two neighboring perspective rays at each plane and is used to determine the number of voxels and weights for these voxels required to compute a single sample at each plane. Multi-resolution datasets prepared for different levels of details are used to simplify the resampling operation by limiting the number of voxels required to compute a single sample.

Parallel volume rendering system with a resampling module for parallel and perspective projections

A system is provided to enhance the capability of a display system which format digital images of different types from multiple input data streams for a high-resolution screen of arbitrary shape and size, with the display system adapted to receive independent data streams from different data sources at the same time and control how and where the images from the data streams are presented on the screen in a type-independent manner. The screen layout is controlled by an active screen format that specifies which data streams are to be received, where on the screen to present the images and how to present the images. Type-independent data formatting is accomplished by choosing the preprocessing handler/transformation handler pair suitable for the type of a data stream and activating the handlers so that they restore images from the data stream and transform them to fit on the preallocated portion of the screen on the fly. In one embodiment, the data stream manager dynamically creates a data stream server for each data stream to maintain data structures for management and preprocess data, and, with the knowledge of the shape and size of the screen, the screen format manager allocates a screen area and creates a screen format server for each data stream to generate images from the data preprocessed by the data stream server by performing the specified transformation on them to fit on the preallocated screen portion.

Data formatting system for processing multiple independent input data

A computer program version update system reduces storage space usage and enables calling programs to invoke any version of a program using the same name by storing only modified modules of a program for different program versions. Multiple versions of a program can thus have the same name. Any version of the program may be constructed from the modules upon command with a user issuing such a command and including a version number corresponding to the requested version as a parameter to invoke a program construction procedure.

Computer program version management system with reduced storage space

A system is provided to increase the efficiency of a VLIW, Very Long Insttion Word, processor which matches its level of parallelism, LOP, to the LOP of the executable code before executing the code's fixed-length VLIW instructions, so that object-level code compatibility is kept for different processor implementations of the same VLIW architecture required for different applications. Matching is accomplished either by reducing the LOP of the processor via inactivating the processor's functional units, or by effectively reducing the LOP of the executable code via the processor executing the sequential portions of each VLIW instruction in the code, with the length of the portions equal to or less than the number of operations that the processor can handle as a VLIW instruction.

Growing community of inventors

Newton, MA, United States of America

Takahide Ohkami