Kabushiki Kaisha Toshiba

Takahide Nishiyama

Tarou Iwashiro

Seiichi Tomita

According to one embodiment, a semiconductor integrated circuit includes an input register which latches, by a second unit, data which are read from a memory cell array by a first unit, a bit state-counter which counts a bit state of the data latched in the input register, a frame size-setup register which latches the first unit, an input data-counter which detects whether or not a total number of the data input to the input register reaches to the first unit, an accumulation circuit which accumulate a value counted by the bit state-counter, a threshold value-register which latches a threshold value for detecting whether or not an erase area of the memory cell array is accessed, a comparison circuit which compares an accumulated value of the accumulation circuit and the threshold value with each other, and a product storage-register which latches a result of the comparison circuit.

Semiconductor integrated circuit

A controller includes an instruction table memory, a program counter, a first decoder, and a first executing unit. The instruction table memory stores an instruction code obtained by coding a sequence to access a nonvolatile semiconductor memory. A read address in the instruction table memory is set to the program counter. The first decoder decodes the instruction code read from the instruction table memory to output a first decode signal. The first executing unit executes access to the nonvolatile semiconductor memory on the basis of the first decode signal output from the first decoder.

Controller which controls operation of nonvolatile semiconductor memory and semiconductor memory device including nonvolatile semiconductor memory and controller therefore

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Yokohama, Japan

Takahide Nishiyama