Kabushiki Kaisha Toshiba

Takahide Mizutani

Masayuki Yoshida

Kazuyoshi Shinada

Teruo Uemura

Naoki Hanada

Yukihiro Saeki

Osamu Matsumoto

Tomohisa Shigematsu

Kenji Toyoda

Nobuyoshi Chida

Hiroyuki Takamura

Tatsuo Mori

A manufacturing method of a semiconductor memory device includes the steps of selectively forming a field oxide film and a gate oxide film on a semiconductor substrate, depositing a first conductive layer on an entire surface of the resultant structure, selectively etching the first conductive layer located in a region other than an element region, depositing a second conductive layer on an entire surface of the resultant structure, and etching the first conductive layer and the second conductive layer using the same mask to form a plurality of floating gates by the first conductive layer and to form a plurality of control gates by the second conductive layer, wherein the step of selectively etching the first conductive layer includes the first etching step of forming cell slits for separating the plurality of floating gates from each other and the second etching step of forming removed regions each of which includes only one end of each of the plurality of control gates.

Manufacturing method for a floating gate semiconductor memory device by

An E.sup.2 PROM and an EPROM are formed on the same substrate. An E.sup.2 PROM memory cell has a floating gate and a control gate. A tunnel insulating film is formed between the floating gate and source/drain regions, thereby constituting a memory cell of an 'FLOTOX' type. An EPROM memory cell has a floating gate and a control gate, thus constituting a memory cell of an 'SAMOS' type.

Semiconductor device having E.sup.2 PROM and EPROM in one chip

A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

Method for manufacturing semiconductor device having a non-volatile

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Yokohama, Japan

Takahide Mizutani